Abov MC96F6332D - SPISR (SPI 2 Status Register)

MC96F6432
June 22, 2018 Ver. 2.9 187
SPISR (SPI 2 Status Register) : B7H
7
6
5
4
3
2
1
0
SPIIFR
WCOL
SS_HIGH
–
FXCH
SSENA
–
–
R/W
R
R/W
–
R/W
R/W
–
–
Initial value : 00H
SPIIFR
When SPI 2 Interrupt occurs, this bit becomes ‘1’. IF SPI 2 interrupt is
enable, this bit is auto cleared by INT_ACK signal. And if SPI 2 Interrupt
is disable, this bit is cleared when the status register SPISR is read, and
then access (read/write) the data register SPIDR. Writing “1” has no
effect.
0
SPI 2 Interrupt no generation
1
SPI 2 Interrupt generation
WCOL
This bit is set if any data are written to the data register SPIDR during
transfer. This bit is cleared when the status register SPISR is read, and
then access (read/write) the data register SPIDR
0
No collision
1
Collision
SS_HIGH
When the SS2 pin is configured as input, if “HIGH” signal comes into the
pin, this flag bit will be set.
0
Cleared when ‘0’ is written
1
No effect when ‘1’ is written
FXCH
SPI 2 port function exchange control bit.
0
No effect
1
Exchange MOSI2 and MISO2 function
SSENA
This bit controls the SS2 pin operation
0
Disable
1
Enable (The P17 should be a normal input)