Ametek UPLC-II - Page 34

Page 2–22
Figure 2–13a. UPLC-II ™Overall Functional Block Diagram
T
ransceiverBoard
EthernetBoard
(Optional)
TX1/RX1
Ethernet
RJ-45or
ST
Fiber
TX2/RX2
TB7-3+
J13MOD J14
TTL
TB7-4
–
J4DNP3
RS-232orRS-485(DB-9)
FrontDisplay
Board
Front
Door
T
O/FROM
I/OBoard
T
O/FROM
I/OBoard
MainPower
Amplifier
RedundantPower
Amplifier
(Optional)
NOTE:
1.
Allsymbolsnotenclosedinanoutlinedbox,arelocatedonthebackplane.
2.
T1actsasacombinerwiththeoptionalredundantP
A
installedandthe1-P
A
jumpersetfor2-P
A.
CoaxBNCConnector
T
erminalBlock
HardwareJumper
CircuitCommon
EXT
CLI
IRIG-BINPUT
BNCFemale
D
KeyingLogic T
ransmitter
Frequency
Selectivity
ReceiverOutputLogic
J1
T
ransmitter
Output
(BNC)
Input
(BNC)
J2
Receiver
Processor
DigitalSignalProcessor
Processor(PPC)
4X20CharacterDisplay
Status
TXFWD
PWR
TXFWD
PWR
TXREFL
PWR
TXREFL
PWR
1
–
P
A
T1
T2
75
W
50
W
2-Wire
4-Wire
Status
XCVRStatus I/OStatus
Aux
Display
Board
Main
Redundant
RS-232
DB-9
RJ-45
Ethernet
D
Key
pad
DC
PWR
ON
DC
PWR
ON
TX
RF
ON
TX
RF
ON
P
A
P
A