Ametek UPLC-II - Segregated Phase Comparison System

January 2016 Page 3–21
Chapter 3. Applications
3
3.5.5 Segregated Phase Comparison
System
The Segregated Phase Comparison system has
been developed to improve pilot relay protection,
particularly for the long EHV series capacitor-
compensated transmission lines. Long EHV series
capacitor-compensated lines are a source of sig-
nificant transients during the fault period. Under
these circumstances, sequence current networks
designed to operate at normal system frequency
may present a problem. The experience with these
Phase Comparison systems has, however, been
remarkably good. Directional Comparison sys-
tems, on the other hand, are subject to mis-opera-
tion on series capacitor-compensated lines, partic-
ularly if the capacitor gaps do not short the capac-
itors on faults. Segregated phase comparison sys-
tems, which are current-only, are independent of
the following phenomena:
• Power system frequency and wave form
• Effects of impedance unbalance between
the power system phase circuits.
• Maximum load/minimum fault current
margin.
The segregated phase comparison system can be
divided into two types: a two-subsystem scheme
and a three-subsystem scheme. In the two-subsys-
tem scheme, one subsystem operates from delta
current (I
a
-I
b
) for all multi-phase faults, and a
ground (3I
0
) current subsystem operates for all
ground faults. The three-subsystem scheme has a
subsystem for each phase (I
a
, I
b
, and I
c
). Each
subsystem consists of one channel (UPLC-II™)
and one Phase Comparison relay.
Both segregated Phase Comparison systems
incorporate “offset keying”, enabling them to trip
for internal high-resistance ground faults and
internal faults with outfeed at one terminal. No
other system can clear these types of faults with-
out extra logic or channels. On a 500 kV line with
a 2,000:5 current transformer ratio, for example,
the three-subsystem scheme will operate for
ground-fault resistances up to about 100 Ω pri-
mary impedance. Under the same conditions, the
two-subsystem scheme will operate up to about
200 Ω primary fault resistance.
The two-subsystem package is suitable for all
applications except single-pole tripping, where the
three-subsystem package must be applied. The
basic operation of the scheme is illustrated in
Figure 3–12. Each current is fed through a nonin-
ductive resistor, supplying a voltage output to the
squaring amplifier (SA) that is exactly proportion-
al to the primary currents. The output of these
amplifiers is used to key the individual channels
and, through the local delay timers (LDT), to pro-
vide the local square waves for comparison. The
timers are adjustable between 2 and 20ms to com-
pensate for the delay time of the channel. This dig-
ital delay circuit translates the pulse train inde-
pendently of the pulse width ratio, in contrast to
the ac phase angle shift used in the other systems.
The ac phase shift delay uses frequency-depen-
dent components, which are accurate only at sys-
tem frequency and can “ring” during transient
conditions.
The square wave comparison is made independ-
ently for each current in the separate subsystems.
Separate channels are required for each of the sub-
systems. One of the comparison circuits is shown
in simplified form in Figure 3–13. In this dual
comparison circuit, AND-P is used for the positive
half-cycles and AND-N for the negative half-
cycles. As shown in Figure 3–13, the received
positive square wave corresponds to a “1” input to
AND-P, and the received negative square wave to
a “0” input, negated to “1”, into AND-N. Except
for this variation, operation is as shown by the
square wave blocks in the lower half of Figure 3–
11.