Ametek UPLC-II - Page 46

Page 2–34
U5
U2
U6
U4
U3
U7
U1
S1
S2
U8
LogicLevel1
1=NOISEOUT
0
1=F
ADE
ALARMOUT
1=F
ADEMARGINOUT
1=
TRIP
POSOUT
1=
TRIP
NEGOUT
Fromreceiverfront-end andchannelbandpass digitalfilter
.
FSdiscriminator
,
amplitudedetector& fastnoisedetector
1=RXSIGNAL
>CENTERFREQ.
0=RXSIGNAL
<CENTERFREQ.
1=NOISE
LOWLEVEL
HOLD
TIMER
0
__________
3ms
NOISEHOLD
TIMER
1=LOW
LEVEL
3ms
__________
0
1=GOOD CHANNEL
OUT
HF=
TP
&LF=
TN
LF=
TP
&HF=
TN
TP
&
TNCLAMPS
T
O1
TP
&
TNCLAMPS
T
O0
POLARITY
CHANNEL
TROUBLE
NOTE:S1andS2arenotrealswitches.
Theyshowprogrammedsettings.
Figure 2–17. FSK Mode: Phase Comparison Logic Diagram