Ametek UPLC-II - Page 52

Page 3–6
UPLC-II™ System Manual
Protected Line
G
H
1 2
Transmitter
Receiver
Channel
Fault Detecting Logic
(Figure 2–2)
Fault Detecting Logic
(Figure 2–2)
Receiver
Output
Receiver
Output
Local
Input
Local
Input
Comparison Circuit
Basic Logic
Arming Arming
Internal Fault (F
I
)
(at Terminal G*)
External Fault (F
E
)
(at Terminal G*)
Local Input
to AND
Receiver
Output
Receiver Input
to AND
AND Output
Trip Output
* Equivalent operation and same trip output at Station H.
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
11
1
1
1
4
0
Comparison Circuit
Basic Logic
4
0
Trip Breaker 1 Trip Breaker 2
Transmitter
Receiver
F
I
& F
E
F
E
F
E
F
I
F
I
AND AND
Figure 3–3.
Single Phase-Comparison Blocking, Current Only Operation