UG-570 AD9361 Reference Manual
| Page 22 of 128
FAST LOCK PROFILES
OVERVIEW
The AD9361 includes a fast lock mode that makes it possible to
achieve faster than normal frequency changes by storing sets of
synthesizer programming information (called profiles) either
into device registers or the BB processor’s memory space to be
recalled at a later time. The fast lock mode eliminates most of
the overhead of synthesizer programming by allowing up to
8 full Rx profiles and 8 full Tx profiles of frequency
configuration information (including VCO calibration results)
to be stored in the device for faster frequency changes.
To use a particular profile, first it must be configured. Typically,
this would be accomplished at power-up, but a new or updated
profile can be defined at any convenient time.
To define a profile, the synthesizer is configured, calibrated, and
allowed to lock at a particular frequency. The VCO calibration
time should be set to the longest, most accurate time period
(FDD mode) since these values are to be stored for future use.
Once the synthesizer has been configured and the VCO
calibration has completed, the baseband processor transfers the
resulting information from the synthesizer registers into the fast
lock memory space by profile number. This is repeated for each
desired profile (0 to 7 Rx and 0 to 7 Tx).
If more than the 8 on-chip profiles are needed, the synthesizer
is tuned and calibrated as if the information were to be stored in
a profile, but instead it is stored in baseband processor memory
space and written into the desired profile at a later, more
convenient time. In this way, an unlimited number of profiles
can be available, and a given profile can be changed or updated
at any appropriate time during operation.
In addition, the user can also define a higher initial charge
pump current and R1 value of the loop filter to increase the
synthesizer’s bandwidth for a programmable amount of time to
further reduce lock time. These values are defined in the profile
information as well.
A profile can be recalled by either issuing a single SPI command
that contains the desired profile number and transfer bit, or
alternatively, a profile can be selected in hardware by setting the
appropriate code on control input pins. At that time, all the
on-chip stored profile information is transferred into the
synthesizer registers, the synthesizer is immediately configured,
and it is released to lock as quickly as the loop BW allows.
FAST LOCK INITIAL WIDER BW OPTION
The fact that the VCO calibration is eliminated in fast lock
may provide fast-enough synthesizer locking for a particular
application. However, when a profile is selected, it is also
possible to initially have different loop filter values and charge
pump current resulting in a wider loop BW for a programmable
time period, possibly resulting in an even faster lock mode.
After the time period expires, the loop filter values take on the
steady state narrow values of the profile. If this feature is not
needed or desired, simply program the init values the same as
the narrow values.
Assuming the same phase margin for wide (init) and narrow
BW is desired,
For a BW Ratio, N = Init BW/Narrow BW,
CP_current_init = CP_current_narrow Ă— N
2
R1_init = R1_narrow/N
In practice, CP_current_init will probably max out before it
could actually be the square of the narrow value. Even though
this occurs, a lock time advantage is still possible; the absolute
values that result in the fastest lock and settling times will need
optimization by the customer during product development.
Note that charge pump currents and all loop filter components
can be completely different between wide (initial) and narrow
values, so exercise care when configuring to result in optimum
and stable performance in both wide and narrow BW modes.
The amount of time the wider BW is active is programmed into
the Fast Lock Setup Init Delay register in increments of 250 ns
per bit.
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