Analog Devices AD9361 User Manual

UG-570 AD9361 Reference Manual
| Page 44 of 128
STATE 2: MEASURE POWER AND LOCK LEVEL GAIN
CHANGE
Upon entering State 2, the AGC waits for a time equal to Settling
Delay minus Energy Detect Count. The subtraction is performed
because the AGC has already waited for the Energy Detect
Counter to expire in order to exit State 1. Thus, the delay before
measuring power does not need to count through this delay
again. After the delay calculated above, the AGC measures
average signal power at the output of the HB1 filter (see the
Average Signal Power section).
The AGC keeps the LMT, ADC, and digital saturation overload
detectors enabled while it is in State 2. If overloads occur, the
AGC will go back to State 1 to reduce the gain.
If the Enable Incr Gain bit is set, then the AGC is allowed to
increase gain if the average signal power stays below the Low
Power Threshold for a time greater than the Increment Time. The
gain step size used Increment Gain Step + 1. The gain continues
to increase until the signal does not remain below the Low Power
Threshold longer than the Increment Time. Figure 25 shows this
as State 2A. The AGC exits State 2A by going back to State 1 to
check again for Peak Overloads.
If the AGC has entered State 2 and does not detect a low power
condition, or the Enable Incr Gain bit is cleared, then the
measured signal power is compared against the AGC Lock Level
(Fast). The AGC then adjusts the gain to match the average signal
power to the AGC Lock Level setting. The lock level is stored in
−dBFS in a resolution of 1 dB/LSB. If the gain needs to increase to
achieve the lock level setting, then there is a maximum amount
that it can increase, set by AGCLL Max Increase.
In the full gain table mode, the AGC simply changes the gain
index such that the signal power matches the lock level (unless
limited by the AGCLL Max Increase). In split table mode, if the
Enable LMT Gain Incr for Lock Level bit is set high, the actions
are per Table 22. If that bit is not set high, then only LPF gain can
be used for gain increases. In addition, regardless of the bit
setting, if a small LMT overload occurs during the lock level
calculation, LMT gain will not be allowed to increase to meet the
lock level.
STATE 3: MEASURE POWER AND PEAK OVERLOAD
DETECT
When the AGC enters State 3, it locks the gain. This state can
affect other portions of the AD9361 such as DC offset tracking
updates and RSSI measurement start times.
The AGC continues to measure power and it keeps its large LMT,
large ADC, and digital saturation overload detectors enabled.
If the Enable Gain Inc After Gain Lock bit is set and the Enable
Incr Gain bit is set, then the AGC will check to see if a Low Power
condition occurs. The method used is the same as that used in
State 2 (including the transition to State 1 if the gain must
increase). If Enable Gain Inc After Gain Lock is clear, then the
AGC does not perform the low power test in State 3. If the AGC
exits State 3 due to a low power condition, the gain unlocks.
If the thresholds have been set correctly, then the overload
detectors should not assert even after the lock level adjustment
unless the signal-of-interest level increases or an out-of-band
blocker is suddenly present. To guard against these possibilities,
the AGC monitors its overload detectors. If overloads occur after
the lock level adjustment, the AGC uses different step sizes to
change the gain.
In full gain table mode, regardless of the type of overload, the step
size (number of indices reduced) is always the Post Lock Level
Step Size for Full Table value. In split gain table mode, the step
size is the Post Lock Level Step Size for LPF Table for ADC
overloads and the Post Lock Level Step for LMT Table for LMT
overloads. These step sizes are usually smaller than those used in
State 1 and State 2. State 1 and State 2 overload step sizes are
designed to respond to large overloads very quickly. The overload
that may occur in State 3 would normally be smaller and require
less adjustment.
STATE 4: UNLOCK GAIN
If these overloads occur, the AGC decreases gain in State 4. The
gain unlocks while the AGC is in State 4. The AGC then returns
to State 3.
The AGC counts the number of overload conditions that occur
after the Lock Level adjustment. If this number exceeds the Final
Overrange Count, then the AGC goes back to State 1 and resets
its peak detectors.
Table 22.Fast Attack AGC Lock Level Gain Index Change for Split Gain Table
If Gain Needs To Do This First And If Then Do This
Decrease Reduce LPF gain index LPF gain index = 0 Reduce LMT gain index
Increase Increase LMT gain up to LMT step size Total gain change > LMT step size Increase LPF gain index
Rev. A

Analog Devices AD9361 Specifications

General

Brand	Analog Devices
Model	AD9361
Category	Motherboard
Language	English