Analog Devices AD9361 User Manual

UG-570 AD9361 Reference Manual
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INITIALIZATION AND CALIBRATION
OVERVIEW
The AD9361 powers up into a sleep state for minimal power consumption. Before the AD9361 is operational, its clocks must be
enabled and initial calibrations completed. The purpose of this section is to describe in detail the operation of the different initialization
calibrations.
Table 1 lists the initialization calibrations documented in this section.
Table 1. Initialization Calibrations Detailed in this Section
Calibration Run Frequency Calibration Done Bit
BBPLL VCO calibration Once; any time BBPLL frequency changes 0x5E[7], 1 when locked
RF synthesizer charge pump
calibration
Once Rx: 0x244[7], 1 when done
Tx: 0x284[7], 1 when done
RF synthesizer VCO calibration
Occurs automatically when integer frequency word written. In TDD, occurs when TXNRX
changes logic level.
Rx: 0x247[1], 1 when locked
Tx: 0x287[1], 1 when locked
Baseband Rx analog filter tune
Once; update when BW changes
0x016[7], self clears when
done
Baseband Tx analog filter tune Once; update when BW changes
0x016[6], self clears when
done
Baseband Tx secondary filter tune Once; manual equations, update when BW changes
Rx TIA calibration Once; manual equations, update when BW changes
Rx ADC setup Once; manual LUT or equations, update when ADC sampling rate changes
Baseband DC offset Once
0x016[0], self clears when
done
RF DC offset Any time LO frequency changes more than 100 MHz
0x016[1], self clears when
done
Rx quadrature calibration Any time LO frequency changes more than 100 MHz Tracking runs continuously
Tx quadrature calibration Any time LO frequency changes more than 100 MHz
0x016[4], self clears when
done
Rev. A

Analog Devices AD9361 Specifications

General

Brand	Analog Devices
Model	AD9361
Category	Motherboard
Language	English