Analog Devices AD9361 User Manual

AD9361 Reference Manual UG-570
| Page 17 of 128
MAIN PLL BLOCK
The independent Rx and Tx PLLs use fractional-N techniques
to achieve the channel synthesis. The entire PLL is integrated
on-chip, including the VCO and the loop filter. The PLL always
operates over the range of 6 GHz 12 GHz. The charge pump
current is programmable as are all of the loop filter components
allowing optimization of performance parameters for almost
any application.
Configuration for a given frequency consists of a combination
of calculating the required divider values and referring to an
Analog Devices supplied lookup table to configure the VCO for
stable performance over temperature. The main PLL output is
divided by the VCO divider block to create the frequency bands
that allow the device to operate continuously from 70 MHz to
6 GHz. Figure 5 shows how the bands are created. The
synthesizer configuration registers, loop filter, integer and
fractional words, and VCO divider are calculated in the
ad9361_rx_lo_freq and ad9361_tx_lo_freq function calls.
Figure 4. PLL Synthesizer Block Diagram (Rx and Tx Synthesizers are Identical)
Fig
ure 5. VCO Divider
8/9
PRE
-
SCALER
Σ-Δ
MODULATOR
LC VCO
PROGRAMMABLE
INTEGRATED LOOP
FILTER
CHARGE
PUMP
PFD
UP
DN
B COUNTER
A COUNTER
FO CAL
ALC CAL
VCO
LDO
2
4
×2
1Ω
1µF
CERAMIC
VCO LDO IN
CONNECTED EXTERNALLY
NECESSARY FOR LDO STABILITY
VCO LDO OUT
VDDA1P1 -VCO
FOR BEST
PERFORMANCE
F
REF
= 35MHz TO 80MHz
F
REF
=
10MHz TO 80MHz
F
REF
=
5MHz TO 320MHz
0.1mA TO 6.4mA
0µA TO 787.5µA
12.5µA STEPS
TO
VCO DIVIDER
BLOCK
6GHz TO 12GHz
100µF
÷
÷
11668-005
MUX/SELECTABLE BUFFERS
÷ 2
÷ 2
÷ 2
÷2
÷2
÷2
÷2
VCO INPUT
6GHz TO 12GHz
I
Q
I
Q
I
Q
I
Q
LO
I
LO
Q
47MHz TO 6GHz
3GHz TO 6GHz 1.5GHz TO 3GHz 750MHz TO 1.5GHz 375MHz TO 750MHz 187.5MHz TO 375MHz 93.75MHz TO 187.5MHz 46.875MHz TO 93.750MHz
11668-006
Rev. A

Analog Devices AD9361 Specifications

General

Brand	Analog Devices
Model	AD9361
Category	Motherboard
Language	English