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General| Brand | Analog Devices |
|---|---|
| Model | AD9361 |
| Category | Motherboard |
| Language | English |
Information about AD9361 registers and driver availability.
Support resources for AD9361 drivers.
Definitions of key terms used in the manual.
Format for describing registers and bits.
Calibration of the Baseband PLL VCO.
Calibration of RF PLL charge pump currents.
Calibration of RF PLL VCOs.
Tuning the Rx anti-aliasing filter.
Tuning the Tx anti-imaging filter.
Programming the Tx secondary filter.
Calibration of the Rx transimpedance amplifier.
Configuration for the receive ADC.
Calibrating baseband DC offset.
Tracking baseband DC offset.
Calibrating RF DC offset.
Minimizing Rx phase and gain error.
Minimizing Tx DC offset, gain, and phase errors.
Setting up and operating the Digitally Controlled Crystal Oscillator.
Setting up and operating the reference clock.
Phase noise requirements for the clock source.
Block diagrams of the AD9361 PLL.
Details of the reference block in the PLL architecture.
The independent Rx and Tx PLL blocks.
Configuring the charge pump current.
Details of the RFPLL loop filter.
Configuring the Voltage Controlled Oscillator.
Process for calibrating the VCO.
Measuring the VCO Vtune voltage.
Configuring the lock detector.
Storing synthesizer programming information for faster frequency changes.
Using wider loop bandwidth for faster lock times.
Selecting fast lock profiles using hardware control pins.
Real-time control of device state using the ENSM.
Definitions of ENSM states.
Controlling the ENSM via SPI or pins.
Controlling the ENSM via SPI.
Steps to enter and exit the sleep state.
Recalibrations needed after waking from sleep.
Description of the AD9361 transmit signal path.
Details of digital filters in the Tx path.
Description of the transmit FIR filter.
Description of the AD9361 receive signal path.
Analog filters before the ADC in the Rx path.
Rx Transimpedance Amplifier Low-Pass Filter.
Rx Baseband Low-Pass Filter.
Digital filters after the ADC in the Rx path.
Rx HB3/DEC3 decimating filter.
Rx HB2 decimating filter.
Rx HB1 decimating filter.
Description of the receive FIR filter.
Calculation of digital Rx block delay.
Overview of gain tables and pointers.
Using a single gain table for all receiver blocks.
Splitting gain tables for improved noise figure.
Adding digital gain to the system.
Manual Gain Control overview.
AGC mode for slowly changing signals.
Timing for AGC gain updates in slow attack mode.
Hybrid AGC mode operation.
Fast attack AGC mode operation.
Initial reset state of the AGC.
Detecting peak overloads and adjusting gain.
Measuring power and changing gain to lock level.
Measuring power and detecting peak overloads.
Reducing gain and unlocking the AGC.
Locking gain and measuring average power.
Overview of modifying gain tables for optimal RF performance.
LNA gain settings based on index.
Mixer gain settings based on index.
TIA gain settings based on index.
LPF gain settings based on index.
Digital gain settings based on index.
Functionality of the RF DC Calibration bit.
Setting the maximum index for gain tables.
Integrating external LNAs with the AD9361.
Selecting RSSI mode and measurement duration.
Weighting RSSI measurements.
RSSI delay and wait settings.
Configuring the RFIR for RSSI measurements.
Calibrating RSSI gain steps.
Overview of transmit power control.
Controls attenuation of the transmit path.
Options for implementing attenuation words.
Overview of the Tx power monitor circuit.
Description of the Tx power monitor circuit.
Matching network for TPM inputs.
Gain control for the Tx power monitor.
Maximizing TPM dynamic range.
Example TxMON configuration for TPM transfer function.
Using TPM test mode for data output.
Defining expected AD9361 port impedance values.
Considerations for Rx interface configuration.
Interfacing with external components.
Maximum input power for Rx LNA.
DC voltage level for Rx LNA input.
Bias voltage for Tx output ports.
Considerations for board layout and matching.
Single-ended and differential interface circuits.
Overview of necessary factory calibrations.
Digitally Controlled Crystal Oscillator setup.
Transmit RSSI measurement calibration.
Receive RSSI measurement calibration.
Calibrating Rx GM/LNA gain steps.
Calibration for Tx power output.
Description of control output bits.
Mapping of control outputs to signals.
Detailed description of control output signals.
Control output for calibration status.
Control output for PLL lock status.
Control output for calibration busy status.
Control outputs for Rx gain control.
Rx gain control outputs.
Rx gain control outputs.
Rx gain control outputs.
Rx gain control outputs.
Rx gain control outputs.
Control signals for Rx/Tx enable and RSSI status.
Control output for digital overflow status.
Control outputs for calibration and ENSM states.
Control outputs related to gain control.
Status of Tx quadrature and RF DC calibration.
Status of Rx quadrature and BB DC calibration.
Control outputs for gain control.
Control signals for gain control and RSSI.
AuxADC digital output data.
Control signals for gain control and power word ready.
Control signals for gain control and power word ready.
Control output for digital overflow status.
Control signals for DC offset tracking.
Control outputs for gain control.
Control outputs for gain control.
Control signals for DC offset tracking and power word ready.
Control outputs for charge pump calibration states.
Control outputs for Rx VCO and ALC calibration states.
Control outputs for Tx VCO and ALC calibration states.
Control outputs for Rx VCO calibration states.
Control outputs for Tx VCO calibration states.
Control signals for gain, temp sense, and AuxADC validity.
Control outputs for gain control.
Description of auxiliary DACs.
Description of auxiliary ADC.
Measuring the internal temperature sensor.
Controlling the general-purpose output pins.
Automatic GPO toggling based on ENSM.
Overview of baseband synchronization.
Synchronizing multiple AD9361 devices.
Procedure for synchronizing multiple devices.
Methods for verifying data synchronization.
Overview of digital interfaces.
CMOS mode interface characteristics.
LVDS mode interface characteristics.
Description of CMOS data path and clock signals.
Description of parallel data ports.
Receive data path master clock.
Feedback clock for transmit data.
Frame signal for receive data.
Frame signal for transmit data.
Signal for controlling data transfer bursts.
Signal for controlling data transfer direction.
Maximum clock rates and signal bandwidths in CMOS mode.
Mode for TDD operation and data rates < 61.44 MHz.
Timing diagrams for single port TDD mode.
Mode for FDD operation and data rates < 30.72 MHz.
Mode for TDD operation and data rates up to 122.88 MHz.
Mode for FDD operation and data rates < 61.44 MHz.
Timing diagrams for dual port FDD LVDS mode.
Timing constraints for LVDS data buses.
Mechanism for digital control of the AD9361.
Configuration of the SPI interface.
Protocol for SPI data transfers.
Format of the SPI instruction word.
Output clock signal for the BBP.
Programmable input signals for real-time control.
Programmable output signals for status.
Input signal for real-time AGC control.
General-purpose output pins.
Hardware reset input signal.
Synchronization input for multiple devices.
Guidelines for PCB material and stack-up.
Guidelines for routing RF transmission lines.
Guidelines for BGA fan-out and trace spacing.
Guidelines for placing critical components and signals.
Analysis of power supply noise effects on performance.
Using an LDO for the 1.3V analog supply.
Using a switching regulator for the 1.3V analog supply.
Analysis of power supply noise effects on phase noise.
Power supply ball assignments and routing.
