UG-570 AD9361 Reference Manual
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TABLE OF CONTENTS
General Information ........................................................................ 1
Revision History ............................................................................... 4
Introduction ...................................................................................... 5
Terminology .................................................................................. 5
Register and Bit Syntax ................................................................ 5
Initialization and Calibration .......................................................... 6
Overview ........................................................................................ 6
Initalization Calibrations ............................................................. 7
BBPLL VCO Calibration ............................................................. 8
RF Synthesizer Charge Pump Calibration ................................ 8
RF Synthesizer VCO Calibration ............................................... 8
Baseband Rx Analog Filter Calibration ..................................... 9
Baseband Tx Analog Filter Calibration ................................... 10
Baseband Tx Secondary Filter .................................................. 11
Rx TIA Calibration Equations .................................................. 11
Rx ADC Setup ............................................................................. 11
Baseband DC Offset Calibration .............................................. 11
Baseband DC Offset Tracking .................................................. 11
RF DC Offset Calibration .......................................................... 12
Rx Quadrature Tracking Calibration ....................................... 13
Tx Quadrature Calibration ....................................................... 13
Reference Clock Requirements ..................................................... 14
Overview ...................................................................................... 14
DCXO Setup and Operation ..................................................... 14
Reference Clock Setup and Operation .................................... 15
Phase Noise Specification .......................................................... 15
RF and BBPLL Synthesizer ............................................................ 16
Overview ...................................................................................... 16
RFPLL Introduction ................................................................... 16
AD9361 PLL Architecture ......................................................... 16
Reference Block .......................................................................... 16
Main PLL Block .......................................................................... 17
Charge Pump Current ............................................................... 18
RFPLL Loop Filter ...................................................................... 18
VCO Configuration ................................................................... 18
VCO Calibration......................................................................... 18
VCO Vtune Measurement ......................................................... 18
Lock Detector .............................................................................. 18
Synthesizer Look Up Table ........................................................ 19
TDD Mode Faster Lock Times ................................................. 19
External LO ................................................................................. 19
Baseband PLL (BBPLL) ............................................................. 19
BBPLL VCO ................................................................................ 20
BBPLL Charge Pump ................................................................. 21
BBPLL Loop Filter ...................................................................... 21
Fast Lock Profiles ............................................................................ 22
Overview ..................................................................................... 22
Fast Lock Initial Wider BW Option ......................................... 22
Configuring and Using a Fast Lock Profile............................. 23
Fast Lock Pin Select ................................................................... 24
Enable State Machine Guide ......................................................... 25
Overview ..................................................................................... 25
ENSM State Definitions............................................................. 25
Modes of Operation ................................................................... 26
Sleep State .................................................................................... 30
Filter Guide...................................................................................... 31
Overview ..................................................................................... 31
Tx Signal Path ............................................................................. 31
Tx Digital Filter Blocks .............................................................. 31
Tx Analog Filter Blocks ............................................................. 32
Rx Signal Path ............................................................................. 33
Rx Analog Filter Blocks ............................................................. 33
Rx Digital Filter Blocks .............................................................. 33
Digital Rx Block Delay ............................................................... 34
Gain Control ................................................................................... 35
Overview ..................................................................................... 35
Gain Control Threshold Detectors .......................................... 36
LMT Overload Detector ............................................................ 36
ADC Overload Detector ........................................................... 36
Low Power Threshold ................................................................ 36
Average Signal Power ................................................................. 36
Settling Times ............................................................................. 37
Peak Overload Wait Time ......................................................... 37
Settling Delay .............................................................................. 37
Gain Table Overview ................................................................. 37
Full Table Mode .......................................................................... 37
Split Table Mode ......................................................................... 38
Digital Gain ................................................................................. 38
MGC Overview .......................................................................... 38
Slow Attack AGC Mode ............................................................ 40
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