Analog Devices AD9361 User Manual

UG-570 AD9361 Reference Manual
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SLEEP STATE
The AD9361 initially powers up in a very low power state called
the SLEEP state. In this state, the AD9361 SPI registers are
powered up; however, all internal clocks and other circuits are
powered down. After power up, the BBP programs the AD9361
using the SPI port and runs the internal calibrations necessary
for optimal performance. After normal transmit/receive
operation, if the AD9361 is not required for radio activity, the
BBP can instruct the AD9361 to return to the SLEEP state to
minimize power consumption.
The SLEEP state is technically the ENSM WAIT state with the
digital clocks turned off. When returning to the SLEEP state, all
calibration results will be stored because the AD9361 SPI
registers remain powered up.
Sleep Procedure (Assumes Current State = ALERT)
1. Disable VCO calibrations to prevent VCO settings from
being overwritten by possible automatic calibrations.
SPIWrite 0x230 = 0x55 Disable Rx VCO
calibration, set 0x230[0]
SPIWrite 0x270 = 0x55 Disable Tx VCO
calibration, set 0x270[0]
2. Move ENSM from ALERT to the WAIT state using the SPI
port. Note that when using FDD, only the Force Tx On bit
controls the ENSM. If using TDD, using Force Rx On will
limit energy being transmitted from the AD9361. In either
case, it is recommended to power down the external PA
before moving the AD9361 into the FDD or Tx states.
SPIWrite 0x014 = 0x00 Clear the To Alert bit in
0x014[0]
SPIWrite 0x014 = 0x20 Move to FDD state (by
setting Force Tx On bit in 0x014[5])
WA I T Wait for FDD flush time
(six ADC_CLK/64 clock cycles)
SPIWrite 0x014=0x00 Move to Wait State (by
clearing 0x014[5])
SPIWrite 0x009=0x00 Turn off all clocks (sleep
state)
3. The AD9361 is now in the SLEEP state.
4. To wake up the AD9361, enable digital clocks and BBPLL,
and then move into the ALERT state.
SPIWrite 0x009 = 0x17 Turn on all clocks
(assumes external clock in this case)
WA I T Wait for BBPLL to lock
(BBPLL lock bit in 0x5E[7], locked =1)
SPIWrite 0x014 = 0x05 Set the To Alert bit and
force Alert state
SPIWrite 0x230 = 0x54 Allow Rx VCO
calibration, clear 0x230[0]
SPIWrite 0x270 = 0x54 Allow Tx VCO
calibration, clear 0x270[0]
Calibrations After Waking from SLEEP
Although the previous calibration results are stored through the
SLEEP state, some calibrations may need to be updated if time
permits. For instance, the AD9361 normally is set to track out
DC offset over time once in the active receive state. The first
time back into the Rx or FDD states, the DC offset may not be
optimal. Running the RF DC Offset Calibration may improve
the DC offset for the first time back in the Rx state. Another
advantage is the calibration stores RF DC offset corrections for
all front-end gain indexes. The tracking mode only allows the
RF DC offset to update at the current gain index.
If using TDD, the Rx VCO and/
or Tx VCO used first will need
to be calibrated before moving into the Rx or Tx state. This can
be accomplished by toggling the TXNRX after enabling VCO
calibrations in Register 0x230 and Register 0x270. The TxRNX
edge triggers the calibration to occur. In FDD, a VCO calibra-
tion should not be required.
Rev. A

Analog Devices AD9361 Specifications

General

Brand	Analog Devices
Model	AD9361
Category	Motherboard
Language	English