UG-570 AD9361 Reference Manual
Rev. A | Page 4 of 128
0x035 = 0x1D (Tx VCO Calibration States) ........................... 80
0x035 = 0x1E (Gain Control, Temp Sense Valid, AuxADC
Valid) ............................................................................................ 81
0x035 = 0x1F (Gain Control) .................................................... 81
AuxADC/AuxDAC/GPO/Temp Sensor ...................................... 82
Overview ...................................................................................... 82
AuxDAC ...................................................................................... 82
AuxADC ...................................................................................... 83
Internal Temperature Sensor .................................................... 84
General Purpose Output Control ............................................. 85
Baseband Synchronization ............................................................ 87
Overview ...................................................................................... 87
Multichip Synchronization ........................................................ 87
Procedure ..................................................................................... 88
Synchronization Verification .................................................... 89
Digital Interface Specification ....................................................... 90
Overview ...................................................................................... 90
CMOS Mode Data Path and Clock Signals ............................. 91
CMOS Maximum Clock Rates and Signal Bandwidths ........ 92
Single Port Half Duplex Mode (CMOS).................................. 93
Single Port TDD Functional Timing (CMOS) ....................... 94
Single Port Full Duplex Mode (CMOS) .................................. 97
Single Port FDD Functional Timing (CMOS) ....................... 99
Dual Port Half Duplex Mode (CMOS).................................. 100
Dual Port TDD Functional Timing (CMOS) ....................... 101
Dual Port Full Duplex Mode (CMOS) .................................. 103
Dual Port FDD Functional Timing (CMOS) ....................... 104
Data Bus Idle and Turnaround Periods (CMOS) ................ 105
Data Path Timing Parameters (CMOS) ................................ 105
LVDS Mode Data Path and Clock Signals ............................ 106
LVDS Mode Data Path Signals ............................................... 107
LVDS Maximum Clock Rates and Signal Bandwidths ....... 108
Dual Port Full Duplex Mode (LVDS) .................................... 109
Data Path Functional Timing (LVDS) ................................... 109
Data Path Timing Parameters (LVDS) .................................. 111
Serial Peripheral Interface (SPI) ............................................. 113
Additional Interface Signals .................................................... 116
Power Supply and Layout Guide ................................................ 117
Overview ................................................................................... 117
PCB Material And Stack Up Selection .................................. 117
RF Transmission Line Layout ................................................. 118
Fan-out and Trace Space Guidelines ..................................... 119
Component Placement and Routing Guidelines ................. 120
Power Management and System Noise Considerations ...... 120
Power Distributions for Different Power Supply Domains 124
Rx LO Frequency Deviations Due to Power Supply
Transients .................................................................................. 126
Related Links ................................................................................. 128
REVISION HISTORY
6/15—Rev. 0 to Rev. A
Change to Table 50 ....................................................................... 108
3/14—Revision 0: Initial Version
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