Analog Devices AD9361 User Manual

UG-570 AD9361 Reference Manual
| Page 34 of 128
Rx FIR
The last digital filter in the Rx signal path is a programmable
poly-phase FIR filter. The Rx FIR filter can also decimate by a
factor of 1, 2, or 4, or it can be bypassed if not needed. The filter
taps are configurable in groups of 16 between a minimum of 16
and a maximum of 128 taps. The taps are in 16-bit 2s
complement format. The Rx FIR also has a programmable gain
of −12 dB, −6 dB, 0 dB, or +6 dB. The filter provides a fixed
+6dB gain to maximize dynamic range, so the programmable
gain is typically set to −6 dB to produce a net gain of 0 dB. Each
coefficient is stored in two registers as a 16-bit number.
The Rx FIR has two options for its sample clock, either
ADC_CLK or ADC_CLK/2. The Rx FIR calculates 16 taps per
clock cycle. This limits the number of available taps to the ratio
of the sample clock to the filter’s output data rate multiplied by
16. For example, if the output data rate is 50 MHz and sample
clock is 200 MHz, then the ratio of the sample clock to the
output data rate is 200/50 or 4. In this scenario, the total
number of taps available is 64.
Unlike the Tx FIR, the Rx FIR has enough internal memory to
allow the maximum number of taps to be used for any
decimation setting. This means that all 128 taps can be used if
the previously described clock ratio is satisfied. This filter is
setup using the ad9361_set_rx_fir_config function.
DIGITAL Rx BLOCK DELAY
The digital Rx filter blocks are designed to minimize delay
caused by mathematical operations so that the total delay is
dominated by the inherent filter delays. Each block’s
contribution to the total data latency is approximated using
the following relationship:
S
data
f
N
t
1
2
×=∆
(13)
wh
ere:
N is the filter order (number of taps)
f
S
is the input sampling clock frequency (before any
decimation).
Example—LTE 10 MHz
In this example, the receiver is set to operate in an LTE 10 MHz
system with a 40 MHz reference clock used. All 128 FIR filter
taps are used, and the data rate is set to 15.36 MSPS. To achieve
this data rate with the given reference clock, each digital filter –
HB3, HB2, HB1, and the FIR filter – have their decimation
factors set to 2. The resulting sample clocks are:
• HB3 (4
th
order filter) − 245.76 MHz
• HB2 (6
th
order filter) − 122.88 MHz
• HB1 (14
th
order filter) − 61.44 MHz
• FIR(128
th
order filter) − 30.72 MHz
The resulting data delay due to digital filtering is
MMMM
t
72.30
1
64
44.61
1
7
88.122
1
3
76.245
1
2 ×+×+×+×=∆
or
μs23.2=∆t
(14)
No
te that the FIR filter is the largest component of this value
due to its large number of taps and lower sampling frequency.
For rough estimate calculations, the half band filters can be
ignored provided the order of the FIR filter is much larger than
the orders of the half band filters.
Rev. A

Analog Devices AD9361 Specifications

General

Brand	Analog Devices
Model	AD9361
Category	Motherboard
Language	English