AD9361 Reference Manual UG-570
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DUAL PORT FULL DUPLEX MODE (LVDS)
Dual bus full duplex LVDS mode is enabled by writing a SPI
register. In this mode, both P0 and P1 are enabled as LVDS
signals and the data buses (D[11:0]) are split into separate sub-
buses (Rx_D[5:0] and Tx_D[5:0]). Each sub-bus operates
simultaneously allowing full duplex of transmit and receive data
between the BBP and the AD9361.
Transmit data (Tx_D[5:0]), FB_CLK, and Tx_FRAME are
driven by the BBP such that the setup and hold times between
FB_CLK, Tx_D[5:0] and Tx_FRAME allow the AD9361 to use
FB_CLK to capture Tx_D[5:0] and Tx_FRAME. The data
samples on the Tx_D[5:0] bus are framed by the Tx_FRAME
signal as shown in the timing diagrams. The transmit data
samples are carried in two’s complement format, with the first
6-bit word in each data packet containing the MSB’s and the
second 6-bit word containing the LSB’s. The most positive
sample value is 0x7FF, with the first word being 0x1F and the
second word being 0x3F, and the most negative value is 0x800,
with the first word being 0x20 and the second word being 0x00.
Tx_D[5] is the most significant bit and Tx_D[0] is the least
significant bit in each word.
Receive data (Rx_D[5:0]), DATA_CLK, and Rx_FRAME are
driven by the AD9361 such that the setup and hold times
between DATA_CLK, Rx_D[5:0] and Rx_FRAME allow the
BBP to use DATA_CLK to capture Rx_D[5:0] and Rx_FRAME.
The data samples on the Rx_D[5:0] bus are framed by the
Rx_FRAME signal as shown in the timing diagrams. The
receive data samples are carried in two’s complement format,
with the first 6-bit word in each data packet containing the
MSBs and the second 6-bit word containing the LSBs. This
means the most positive sample value is 0x7FF, with the first
word being 0x1F and the second word being 0x3F, and the most
negative value is 0x800, with the first word being 0x20 and the
second word being 0x00. Rx_D[5] is the most significant bit
and D[0] as the least significant bit in each word.
Note that, like in CMOS mode, FB_CLK must be generated
from DATA_CLK so that it retains the same frequency and duty
cycle. There is no phase relationship requirement between the
two clock signals.
As mentioned previously, the I and Q data samples are time-
interleaved on each data bus. For a 1R1T system, the I and Q
samples are carried in a 4-way interleave:
I
MSB
, Q
MSB
, I
LSB
, Q
LSB
, …
For this case, the Tx_FRAME and Rx_FRAME signals are
coincident with data switching. Each is in a high state for I
MSB
and Q
MSB
and a low state for I
LSB
and Q
LSB
when 50% duty cycle
framing is enabled. These signals then switch high again with
I
MSB
to indicate the start of a new frame.
For a 2R2T system, the I and Q samples from RF path 1 and 2
are carried in an 8-way interleave:
I
1 MSB
, Q
1 MSB
, I
1 LSB
, Q
1 LSB
, I
2 MSB
, Q
2 MSB
, I
2 LSB
, Q
2 LSB
, …
For this case, the Tx_FRAME and Rx_FRAME signals are
coincident with data switching. Each is in a high state for I
1MSB
,
Q
1MSB
, I
1LSB
, Q
1LSB
and a low state for I
2MSB
, Q
2MSB
, I
2LSB
and Q
2LSB
when 50% duty cycle framing is enabled. These signals then
switch high again with I
AMSB
to indicate the start of a new frame.
For a system with a 2R1T or a 1R2T configuration, the clock
frequencies, bus transfer rates and sample periods, and data
capture timing are the same as if configured for a 2R2T system.
However, in the path with only a single channel used, the
disabled channel’s I-Q pair in each data group is unused. These
unused slots are ignored by the AD9361. As an example, for a
2R1T system using Tx channel 1, the transmit burst would have
four unused slots:
I
1 MSB
, Q
1 MSB
, I
1 LSB
, Q
1 LSB
, X, X, X, X, …
For this case, the Tx_FRAME and Rx_FRAME are coincident
with data switching and high for I
1MSB
, Q
1MSB
, I
1LSB
, Q
1LSB
and
then low for unused slots. These signals then switch high again
with I
1MSB
to indicate the start of a new frame. The unused X
slots may be filled with arbitrary data values by the BBP. Such
values could be either constant values, or the preceding data
sample values can be repeated to reduce the bus switching
factor and, therefore, power consumption.
DATA PATH FUNCTIONAL TIMING (LVDS)
The timing diagrams in Figure 79 and Figure 80 illustrate the
relationship among the bus signals in dual port FDD LVDS
mode. The differential data in the timing diagrams are drawn
with solid and dashed lines to illustrate the differential nature of
the data lines. Solid lines for the positive leg match solid lines
for the negative leg of the differential pair, and dashed lines for
the positive leg pair with dashed lines for the negative leg. Note
that because 2R1T and 1R2T systems follow the 2R2T timing
diagrams, they are omitted from Figure 79 and Figure 80.
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