UG-570 AD9361 Reference Manual
| Page 92 of 128
ENABLE
ENABLE is driven from the BBP to the AD9361 to provide data
transfer burst control (along with TXNRX) in TDD mode.
ENABLE is asserted by the BBP for a minimum of a single
DATA_CLK cycle to indicate the start of each burst. It is
subsequently asserted a second time for a minimum of a single
DATA_CLK cycle to indicate the end of each burst.
The AD9361 internally tracks the sequence of ENABLE pulses
to interpret each pulse correctly as either the start or finish of
each burst. The ENABLE signal also can be configured in level
mode, in which an edge transition (not pulses) determines
when the ENSM moves between states. The level sampled on
TXNRX during each ENABLE start event controls the bus
direction in TDD mode. The start and finish latencies (between
the ENABLE pulses being sampled by the AD9361 and the
presence of the first and last valid data samples on the bus) vary
depending on data path configuration. The RX_FRAME and
TX_FRAME signals are used to determine valid data by the
BBP and the AD9361, respectively. The FB_CLK signal is used
to sample this input.
In FDD mode, the ENABLE signal serves as the single control
input to determine the state of the ENSM. There is also an
alternative FDD mode in which the ENABLE signal can be
redefined as RxON, a direct hardware control input to the
ENSM that controls the Rx function. In this mode (called FDD
independent control mode), the BBP independently controls
the Rx function, which can result in power consumption
savings.
TXNRX
TXNRX is driven from the BBP to the AD9361 and provides
data transfer burst control (along with ENABLE) when the data
bus is in TDD mode. When ENABLE is sampled high by the
AD9361 to start a burst, the level on TXNRX is also sampled to
determine the data direction. In TDD mode, TXNRX sampled
high indicates a transmit burst and TXNRX sampled low
indicates a receive burst.
The TXNRX signal level must be maintained throughout a data
transfer burst (a valid logic level). The TXNRX signal may be
established any number of cycles (≥ 0) before the ENABLE start
pulse is sampled, and it may be changed any number of cycles
(≥ 0) after the ENABLE finish pulse is sampled. It is important
to note that the TXNRX signal should only change state while
the ENSM is in the ALERT state because the TXNRX signal
powers up and down the synthesizers directly in TDD mode.
In normal FDD mode, the TXNRX signal is ignored but must
be held at a valid logic level. There is also an alternative FDD
mode in which the TXNRX signal can be redefined as TxON, a
direct hardware control input to the ENSM that controls the Tx
function. In this mode (called FDD independent control mode),
the BBP independently controls the Tx function, which can
result in power consumption savings.
CMOS MAXIMUM CLOCK RATES AND SIGNAL
BANDWIDTHS
The data listed in Table 48 compares the maximum data clock
rates and maximum RF signal bandwidths in the different
allowable operating modes for the CMOS data bus
configuration. Maximum RF bandwidths are listed for two
cases: sampling using the minimum sample rate that avoids
aliasing, and sampling using 2× oversampling. Details of each
mode are given in subsequent sections. The maximum
DATA_CLK rate is limited to 61.44 MHz, so the data rates are
limited by this factor and the 56 MHz maximum analog filter
bandwidth.
Table 48. Maximum Data Rates (SDR and DDR) and Signal Bandwidths
Operating
Mode
1R1T Configurations 1R2T/2R1T/2R2T Configurations
Maximum Data Rate
(Combined I and Q
Words)
Maximum RF Channel Signal
Bandwidth
Maximum Data Rate
(Combined I and Q
Words)
Maximum RF Channel Signal
Bandwidth (Per Channel)
Using Minimum
Sample Frequency
Using 2×
Oversampling
Using Minimum
Sample Frequency
Using 2×
Oversampling
SDR
(MSPS)
DDR
(MSPS)
SDR
Bus
(MHz)
DDR
Bus
(MHz)
SDR
Bus
(MHz)
DDR
Bus
(MHz)
SDR
(MSPS)
DDR
(MSPS)
SDR
Bus
(MHz)
DDR
Bus
(MHz)
SDR
Bus
(MHz)
DDR
Bus
(MHz)
Single Port
Half Duplex
30.72 61.44 30.72
56
1
15.36 30.72 15.36 30.72 15.36 30.72 7.68 15.36
Single Port
Full Duplex
15.36 30.72 15.36 30.72 7.68 15.36 7.68 15.36 7.68 15.36 3.84 7.68
Dual Port
Half Duplex
61.44 122.88 56
1
56
1
30.72
56
1
30.72 61.44 30.72
56
1
15.36 30.72
Dual Port Full
Duplex
30.72 61.44 30.72
56
1
15.36 30.72 15.36 30.72 15.36 30.72 7.68 15.36
1
Limited by the analog filter bandwidth.
To Next Page
Loading...
Need help?
General
