Eaton EMR-3MP0 - Page 214

LogicMain_E03
AND ORAND OR
Fig. 52: Available gates with the LE[x] modules.
Input Signals
The user can assign up to four Input signals (from the assignment list) to the inputs of the
gate.
As an option, each of the four input signals can be inverted (negated).
Timer Gate (On Delay and O󰃠 Delay)
The output of the gate can be delayed. The user has the option to set an On and an O󰊍
delay.
Latching
The timer issues an unlatched and a latched signal. The latched signal consists of two
outputs, the latched signal and the inverted latched signal.
In order to reset the latched signal, the user has to assign a reset signal from the
assignment list. Optionally, the reset signal can also be inverted. The latching works
based on reset priority. That means, the reset input is dominant.
If no »Reset Latched« signal is assigned, then the »Latch Out« signal will be identical with
the »Timer Out« signal.
Cascading Logical Outputs
The device will evaluate output states of the logic equations starting from “Logic
Equation 1” up to the logic equation with the highest number. This evaluation cycle will
be continuously repeated.
Cascading Logic Equations in an ascending sequence
Cascading in an ascending sequence means that the user utilizes the output signal of
“Logic Equation n” as input of “Logic Equation n+1”. If the state of “Logic Equation n”
changes, the state of the output of “Logic Equation n+1” will be updated within the same
cycle.
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6 Programmable Logic