Freescale Semiconductor MC68332 - Page 262

MC68332
USER’S MANUAL I-1
–A–
Address bus 4-18
Address registers
fault 5-20
general-purpose 5-1
Address strobe (AS) 4-18
Addressing modes 5-8
Addressing range 5-8
Address-mark wakeup 6-30
AS 4-18
Autovector signal (AVEC) 4-20
AVEC 4-20, 4-48, 4-53, 4-55
–B–
Baud rate, SCK 6-17
BCD 5-4
BDM 5-17
BERR 4-5, 4-20, 4-48
BG 4-53
BGACK 4-53
Binary-coded decimal (BCD) 5-4
BITS 6-21
Bit-time 6-25
BKPT 4-28, 4-41, 5-9
BLKSZ 4-53
BMT 4-5
BR 4-53
Break frame 6-26
Break frames 6-28
Bus error signal (BERR) 4-5, 4-20
Bus monitor timing (BMT) 4-5
BYTE 4-54
–C–
C 5-5
Call user code (CALL) 5-20
Carry (C) 5-5
CCR 5-5
Central processing unit (CPU) 3-1
Channel interrupt enable register (CIER) 7-14
Channel interrupt request level (CIRL) 7-5
Channel interrupt status register (CISR) 7-11, 7-14
Chip select pin assignment register 1 (CSPAR1) 4-15
Chip selects
peripheral 6-22
Chip-select
block 4-1
Chip-select operation 4-55
Chip-select pins 4-51
CIER 7-14
CIRL 7-5
CISR 7-11, 7-14
Clock mode (MODCLK) 4-10
Clock synthesizer control register (SYNCR) 4-10
Command RAM 6-8
Completed queue pointer 6-9
Condition code register 5-5
Condition codes 5-5
Control registers
QSPI 6-7
SCI 6-22
CPHA 6-17
CPOL 6-17
CPTQP 6-9, 6-20
CPU 1-1, 3-1
CPU32 1-1, 5-1
CPU32 Registers 2-2
CSBARBT 4-53
CSBOOT 4-40, 4-53, 4-57
CSPAR1 4-15
Current instruction program counter (PCC) 5-20
–D–
Data and size acknowledge signals (DSACK) 4-19
Data bus 4-18
Data frame 6-26
Data register 5-3, 5-4
Data registers
multifunction 5-1
SCI 6-25
Data strobe (DS) 4-18
DDQS1 6-4
DDRE 4-58
DDRF 4-58
DDRQS 6-4, 6-17, 6-21
Delay after transfer 6-19
Discrete I/O 4-58
Double buffering 6-27, 6-28
DS 4-18
DSACK 4-19, 4-48, 4-53, 4-54, 4-55
DSCK 6-18
–E–
EBI 4-1, 4-17, 4-56
EBI transfers 4-56
INDEX
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