Intel 815 - Page 10

R
10 Intel
®
815 Chipset Platform Design Guide
Tables
Table 1. Processor Considerations for Universal Socket 370 Design...............................29
Table 2. GMCH Considerations for Universal Socket 370 Design ....................................30
Table 3. ICH Considerations for Universal Socket 370 Design.........................................30
Table 4. Clock Synthesizer Considerations for Universal Socket 370 Design ..................31
Table 5. Determining the Installed Processor via Hardware Mechanisms ........................35
Table 6. Intel
®
Pentium
®
III Processor AGTL/AGTL+ Parameters for Example
Calculations ................................................................................................................44
Table 7. Example T
FLT_MAX
Calculations for 133 MHz Bus
1
..............................................45
Table 8. Example T
FLT_MIN
Calculations (Frequency Independent) ....................................45
Table 9. Trace Guidelines for Figure 19
1, 2, 3
....................................................................46
Table 10. Trace Width:Space Guidelines..........................................................................46
Table 11. Routing Guidelines for Non-AGTL/Non-AGTL+ Signals....................................49
Table 12. Processor Pin Definition Comparison................................................................52
Table 13. Resistor Values for CLKREF Divider (3.3V Source)..........................................57
Table 14. RESET#/RESET2# Routing Guidelines (see Figure 25)...................................58
Table 15. Component Recommendations – Inductor........................................................61
Table 16. Component Recommendations – Capacitor .....................................................61
Table 17. Component Recommendation – Resistor .........................................................61
Table 18. System Memory 2-DIMM Solution Space..........................................................71
Table 19. System Memory 3-DIMM Solution Space..........................................................74
Table 20. AGP 2.0 Signal Groups .....................................................................................83
Table 21. AGP 2.0 Data/Strobe Associations....................................................................83
Table 22. AGP 2.0 Routing Summary ...............................................................................87
Table 23. AGP 2.0 Routing Summary ...............................................................................91
Table 24. TYPDET#/VDDQ Relationship ..........................................................................93
Table 25. Connector/Add-in Card Interoperability .............................................................98
Table 26. Voltage/Data Rate Interoperability.....................................................................98
Table 27. AC’97 Configuration Combinations .................................................................119
Table 28. Intel
®
CK-815 (2-DIMM) Clocks.......................................................................131
Table 29. Intel
®
CK-815 (3-DIMM) Clocks.......................................................................133
Table 30. Simulated Clock Routing Solution Space ........................................................136
Table 31. Simulated Clock Skew Assumptions ...............................................................138
Table 32. Power Delivery Terminology............................................................................141
Table 33. Power Sequencing Timing Definitions.............................................................151
Table 34. Recommendations For Unused AGP Port ......................................................159