Intel 815 - Figure 74. S0-S3-S0 Transition

Power Delivery
R
Intel
®
815 Chipset Platform Design Guide 149
Figure 74. S0-S3-S0 Transition
DRAM active
DRAM in STR (CKE low) DRAM active
Clocks valid Clocks invalid Clocks valid
t16t15
t9
t22
t8
t23t21
t17
t13
t12
t11t20
t19
t7t18
t24
Vcc3.3sus
RSMRST#
STPCLK#
Stop grant cycle
CPUSLP#
Go_C3 from ICH
Ack_C3 from GMCH
DRAM
SUS_STAT#
PCIRST#
Cycle 1 from GMCH
Cycle 1 from ICH
Cycle 2 from GMCH
Cycle 2 from ICH
CPURST#
SLP_S3#
SLP_S5#
PWROK
Vcc3.3core
Clocks
Freq straps
Wake event
pwr_S0-S3-S0_trans