Intel 815 - Default Chapter; Table of Contents

R
Intel
®
815 Chipset Platform Design Guide 3
Contents
1
Introduction ........................................................................................................................13
1.1 Terminology ..........................................................................................................14
1.2 Reference Documents ..........................................................................................16
1.3 System Overview ..................................................................................................16
1.3.1 System Features ...................................................................................17
1.3.2 Component Features.............................................................................18
1.3.2.1 Graphics Memory Controller Hub (GMCH) ..........................18
1.3.2.2 Intel
®
82801AA I/O Controller Hub (ICH) .............................20
1.3.2.3 Firmware Hub (FWH)...........................................................20
1.3.3 Platform Initiatives .................................................................................21
1.3.3.1 Universal Socket 370 Design...............................................21
1.3.3.2 PC 133 .................................................................................21
1.3.3.3 Accelerated Hub Architecture Interface ...............................21
1.3.3.4 Internet Streaming SIMD Extensions...................................21
1.3.3.5 AGP 2.0................................................................................21
1.3.3.6 Manageability .......................................................................22
1.3.3.7 AC’97 ...................................................................................23
1.3.3.8 Low-Pin-Count (LPC) Interface............................................23
2 General Design Considerations.........................................................................................25
2.1 Nominal Board Stackup ........................................................................................25
3 Component Quadrant Layouts...........................................................................................27
4 Universal Socket 370 Design ............................................................................................29
4.1 Universal Socket 370 Definitions ..........................................................................29
4.2 Processor Design Requirements ..........................................................................31
4.2.1 Use of Universal Socket 370 Design with Incompatible GMCH............31
4.2.2 Identifying the Processor at the Socket.................................................32
4.2.3 Setting the Appropriate Processor VTT Level .......................................33
4.2.4 VTT Processor Pin AG1 ........................................................................34
4.2.5 Identifying the Processor at the GMCH.................................................34
4.2.6 Configuring Non-VTT Processor Pins ...................................................36
4.2.7 VCMOS Reference................................................................................37
4.2.8 Processor Signal PWRGOOD...............................................................38
4.2.9 APIC Clock Voltage Switching Requirements .......................................39
4.2.10 GTLREF Topology and Layout..............................................................40
4.3 Power Sequencing on Wake Events ....................................................................41
4.3.1 Gating of Intel
®
CK-815 to VTTPWRGD ...............................................41
4.3.2 Gating of PWROK to ICH......................................................................42
5 System Bus Design Guidelines .........................................................................................43
5.1 System Bus Routing Guidelines ...........................................................................43
5.1.1 Initial Timing Analysis ............................................................................43