System Bus Design Guidelines
R
Intel
®
815 Chipset Platform Design Guide 59
5.9 Processor PLL Filter Recommendations
Intel PGA370 processors have internal phase lock loop (PLL) clock generators that are analog and
require quiet power supplies to minimize jitter.
5.9.1 Topology
The general desired topology for these PLLs is shown in Figure 27. Not shown are the parasitic
routing and local decoupling capacitors. Excluded from the external circuitry are parasitics
associated with each component.
5.9.2 Filter Specification
The function of the filter is to protect the PLL from external noise through low-pass attenuation.
The low-pass specification, with input at VCC
CORE
and output measured across the capacitor, is as
follows:
• < 0.2 dB gain in pass band
• < 0.5 dB attenuation in pass band (see DC drop in next set of requirements)
• > 34 dB attenuation from 1 MHz to 66 MHz
• > 28 dB attenuation from 66 MHz to core frequency
The filter specification is graphically shown in Figure 26.
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