Intel 815 - Motherboard Layout Rules for Non-AGTL;AGTL+ (CMOS) Signals; Table 11. Routing Guidelines for Non-Agtl;Non-AGTL+ Signals

System Bus Design Guidelines
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Intel
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815 Chipset Platform Design Guide 49
5.2.1.1 Motherboard Layout Rules for Non-AGTL/AGTL+ (CMOS) Signals
Table 11. Routing Guidelines for Non-AGTL/Non-AGTL+ Signals
Signal Trace Width Spacing to Other Traces Trace Length
A20M# 5 mils 10 mils 1” to 9”
FERR# 5 mils 10 mils 1” to 9”
FLUSH# 5 mils 10 mils 1” to 9”
IERR# 5 mils 10 mils 1” to 9”
IGNNE# 5 mils 10 mils 1” to 9”
INIT# 5 mils 10 mils 1” to 9”
LINT[0] (INTR) 5 mils 10 mils 1” to 9”
LINT[1] (NMI) 5 mils 10 mils 1” to 9”
PICD[1:0] 5 mils 10 mils 1” to 9”
PREQ# 5 mils 10 mils 1” to 9”
PWRGOOD 5 mils 10 mils 1” to 9”
SLP# 5 mils 10 mils 1” to 9”
SMI# 5 mils 10 mils 1” to 9”
STPCLK 5 mils 10 mils 1” to 9”
THERMTRIP# 5 mils 10 mils 1” to 9”
NOTE: Route these signals on any layer or combination of layers.