Introduction
R
Intel
®
815 Chipset Platform Design Guide 19
• Accelerated Graphics Port (AGP) Interface
Supports AGP 2.0, including 4X AGP data transfers, but not the 2X/4X Fast Write
protocol
AGP universal connector support via dual-mode buffers to allow AGP 2.0 3.3V or 1.5V
signaling
32-deep AGP request queue
AGP address translation mechanism with integrated fully associative 20-entry TLB
High-priority access support
Delayed transaction support for AGP reads that can not be serviced immediately
AGP semantic traffic to the DRAM is not snooped on the system bus and is therefore not
coherent with the processor caches
• Integrated Graphics Controller
Full 2D/3D/DirectX acceleration
Texture-mapped 3D with point sampled, bilinear, trilinear, and anisotropic filtering
Hardware setup with support for strips and fans
Hardware motion compensation assist for software MPEG/DVD decode
Digital Video Out interface adds support for digital displays and TV-Out
PC99A/PC2001 compliant
Integrated 230 MHz DAC
• Integrated Local Graphics Memory Controller (Display Cache)
0 MB to 4 MB (via Graphics Performance Accelerator) using zero, one, or two parts
32-bit data interface
133 MHz memory clock
Supports ONLY 3.3V SDRAMs
• Packaging/Power
544 BGA with local memory port
1.85V (± 3% within margins of 1.795V to 1.9V) core and mixed 3.3V, 1.5V, and
AGTL/AGTL+ I/O
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