Intel 815 - Page 5

R
Intel
®
815 Chipset Platform Design Guide 5
7.3.2.2
AGP-Only Motherboard Guidelines......................................86
7.3.3 AGP Routing Guideline Considerations and Summary.........................87
7.3.4 AGP Clock Routing ...............................................................................88
7.3.5 AGP Signal Noise Decoupling Guidelines.............................................88
7.3.6 AGP Routing Ground Reference...........................................................89
7.4 AGP Down Routing Guidelines.............................................................................90
7.4.1 1X AGP Down Option Timing Domain Routing Guidelines ...................90
7.4.2 2X/4X AGP Down Timing Domain Routing Guidelines .........................90
7.4.3 AGP Routing Guideline Considerations and Summary.........................91
7.4.4 AGP Clock Routing ...............................................................................92
7.4.5 AGP Signal Noise Decoupling Guidelines.............................................92
7.4.6 AGP Routing Ground Reference...........................................................92
7.5 AGP 2.0 Power Delivery Guidelines .....................................................................93
7.5.1 VDDQ Generation and TYPEDET#.......................................................93
7.5.2 VREF Generation for AGP 2.0 (2X and 4X) ..........................................95
7.6 Additional AGP Design Guidelines........................................................................97
7.6.1 Compensation .......................................................................................97
7.6.2 AGP Pull-Ups ........................................................................................97
7.6.2.1 AGP Signal Voltage Tolerance List......................................98
7.7 Motherboard / Add-in Card Interoperability...........................................................98
7.8 AGP / Display Cache Shared Interface.................................................................99
7.8.1 GPA Card Considerations .....................................................................99
7.8.1.1 AGP and GPA Mechanical Considerations..........................99
7.8.2 Display Cache Clocking.......................................................................100
7.9 Designs That Do Not Use The AGP Port............................................................100
8 Integrated Graphics Display Output.................................................................................101
8.1 Analog RGB/CRT................................................................................................101
8.1.1 RAMDAC/Display Interface .................................................................101
8.1.2 Reference Resistor (Rset) Calculation................................................103
8.1.3 RAMDAC Board Design Guidelines ....................................................103
8.1.4 RAMDAC Layout Recommendations ..................................................105
8.1.5 HSYNC/VSYNC Output Guidelines.....................................................105
8.2 Digital Video Out .................................................................................................106
8.2.1 DVO Interface Routing Guidelines ......................................................106
8.2.2 DVO I
2
C Interface Considerations.......................................................106
8.2.3 Leaving the DVO Port Unconnected ...................................................106
9 Hub Interface ...................................................................................................................107
9.1.1 Data Signals ........................................................................................108
9.1.2 Strobe Signals .....................................................................................108
9.1.3 HREF Generation/Distribution.............................................................108
9.1.4 Compensation .....................................................................................109
10 I/O Subsystem .................................................................................................................111
10.1 IDE Interface .......................................................................................................111
10.1.1 Cabling and Motherboard Requirements ............................................111
10.2 Cable Detection for Ultra ATA/66........................................................................113
10.2.1 Host Side Cable Detection ..................................................................114
10.2.2 Device Side Cable Detection...............................................................115
10.2.3 Primary IDE Connector Requirements ................................................116
10.2.4 Secondary IDE Connector Requirements ...........................................117