Checklist Item Complete?
13
To avoid configuration failures, disconnect the PMBus regulator’s JTAG download cable before configuring Intel Agilex -V devices.
☐
14
If the SDM Debug Toolkit is not operational, verify that the Intel Agilex device has exited POR by checking nCONFIG, nSTATUS,
CONF_DONE and INIT_DONE pins using an oscilloscope.
☐
15
Is the configuration clock source chosen appropriately? You can use an internal oscillator or the OSC_CLK_1 pin.
☐
16
For designs driving the OSC_CLK_1 pin is the frequency 25, 100, or 125 MHz?
☐
17 For Intel Agilex SX parts ensure that the HPS and EMIF IOPLL are stable and free running before configuration begins. The actual
frequency should match the setting specified in Platform Designer.
☐
18 Are proper slave addresses set for the PMBus voltage regulator modules using the Intel Quartus Prime Software? ☐
19 For designs that use 3 V I/0, verify that the transceiver tiles are powered up before configuration begins. ☐
Related Information
Intel Agilex Power Management User Guide
6.2. Intel Agilex Configuration Architecture Overview
Intel Agilex devices employ configuration architecture that is quite similar to the Intel Stratix 10 architecture. The Secure
Device Manager (SDM), a dedicated hard processor, controls and monitors all aspects of device configuration from device
power-on reset. This configuration architecture is different from earlier Intel FPGA device families where state machines
control configuration.
There are important differences between Intel Agilex and Intel Stratix 10 devices and previous device families with respect to
available configuration modes, configuration pin behavior, and connection guidelines. In addition, the bitstream format is
different. Knowing about these differences and how these pins behave can help you understand and debug configuration
issues.
6. Intel Agilex Debugging Guide
UG-20205 | 2019.10.09
Intel
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Configuration User Guide
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