This configuration scheme includes the following steps:
1. In the Intel Quartus Prime Programmer, select the JTAG programming mode and initiate programming by clicking Start.
2.
The Programmer drives .jic configuration data to the board using the JTAG header connection.
3. The programmer first configures the SDM with configuration firmware. Then, the SDM drives configuration data from the
programmer to the AS x4 flash device using SDM_IOs.
4.
To use the Intel Agilex device in AS mode after successful programming of the flash device, set the MSEL pins to either AS
fast or AS normal mode and power cycle the device.
The Intel Quartus Prime Programmer interfaces to the SDM device through JTAG interface and programs the serial flash
device.
3.2.7. Serial Flash Memory Layout
Serial flash devices store the configuration data in sections.
The following diagram illustrates sections of a non-HPS Intel Agilex configuration data mapping in a serial flash device. Refer
to Intel Agilex SoC FPGA Bitstream Sections of the HPS Technical Reference Manual for more information about flash memory
layout for HPS devices.
Figure 42. Serial Flash Memory Layout Diagram
Firmware section
is dependent on
the Quartus Prime
Programmer version
32’d512k
Start Address 32’d0
32’1024k
32’d1536k
32’d2048k
End Address
(Design dependent)
Dynamic Section (I/O Configuration)
Dynamic Section ( FPGA Core Configuration)
Firmware Section
Firmware Section
Firmware Section
Firmware Section
3. Intel Agilex Configuration Schemes
UG-20205 | 2019.10.09
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