Notes for Figure:
1. Refer to MSEL Settings for the correct resistor pull-up and pull-down values for all configuration schemes.
2.
The MSEL pins are dual-purpose. After power-on, you can reassign these pins to other functions. For more information,
refer to Enabling Dual Purpose Pins
3. The synchronizers shown in all three figures can be internal if the host is an FPGA or CPLD. If the host is a microprocessor,
you must use discrete synchronizers.
Related Information
MSEL Settings on page 27
3.1.6. Debugging Guidelines for the Avalon-ST Configuration Scheme
The Avalon-ST configuration scheme replaces the previously available in fast passive parallel (FPP) modes. This configuration
scheme retains similar functionality and performance. Here are the important differences:
•
The Avalon-ST configuration scheme requires you to monitor the flow control signal, AVST_READY. The AVST_READY
signal indicates if the device can receive configuration data.
•
The AVST_CLK and AVSTx8_CLK clock signals cannot pause when configuration data is not being transferred. Data is not
transferred when AVST_READY and AVST_VALID are low. The AVST_CLK and AVSTx8_CLK clock signals must run
continuously until CONF_DONE asserts.
Debugging Suggestions
Review the general Configuration Debugging Checklist in the Debugging Guide chapter before considering these debugging
tips that pertain to the Avalon-ST configuration scheme.
•
Only assert AVST_VALID after the SDM asserts AVST_READY.
•
Only assert AVST_VALID when the AVST_DATA is valid.
•
Ensure that the AVST_CLK clock signal is continuous and free running until configuration completes. The AVST_CLK can
stop after CONF_DONE asserts. The initialization state does not require the AVST_CLK signal.
•
If using x8 mode, ensure that you use the dedicated SDM_IO pins for this interface (clock, data, valid and ready).
• If using x16 or x32 mode, power the I/O bank containing the x16 or x32 pins (I/O Bank 3A) at 1.8 V.
3. Intel Agilex Configuration Schemes
UG-20205 | 2019.10.09
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Configuration User Guide
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