Intel Agilex User Manual

Note:
nSTATUS does not go low for PR failures or failures using the JTAG configuration scheme.
Generally, the Intel Agilex device changes the value of nSTATUS to follow the value of nCONFIG, except after an error. For
example, after POR, nSTATUS asserts after nCONFIG asserts. When the host drives nCONFIG high, the Intel Agilex device
drives nSTATUS high.
In previous device families the deassertion of nSTATUS indicates the device is ready for configuration. For Intel Agilex
devices, when using Avalon-ST configuration scheme, after the Intel Agilex device drives nSTATUS high, you must also
monitor the AVST_READY signal to determine when the device is ready to accept configuration data.
nSTATUS asserts if an error occurs during configuration. The pulse ranges from 0.5 ms to 10 ms.
nSTATUS assertion is asynchronous to data error detection. Intel Agilex devices do not support the auto-restart
configuration after error option.
Previous device families implement the nSTATUS as an open drain with a weak internal pull-up. Intel Agilex always drives
nSTATUS. Consequently, you cannot wire OR an Intel Agilex nSTATUS signal with the nSTATUS signal from earlier device
families.
Debugging Suggestions
Ensure nSTATUS acknowledges nCONFIG. If nSTATUS is not following nCONFIG, the FPGA may not have exited POR. You may
need to power cycle the PCB.
6.7.3. CONF_DONE and INIT_DONE
For Intel Agilex devices, both CONF_DONE and INIT_DONE share multiplexed SDM_IO pins. Previous device families
implement the CONF_DONE and INIT_DONE pins as open drains with a weak internal pull-up. Consequently, you cannot wire
OR an Intel Agilex CONF_DONE or INIT_DONE signal with the nSTATUS signal from previous device families. Otherwise,
CONF_DONE and INIT_DONE behave as these signals behaved in earlier device families. If you assign CONF_DONE and
INIT_DONE to SDM_IO16 and SDM_IO0, weak internal pull-downs pull these pins low at power-on reset. Ensure you specify
these pins in the Intel Quartus Prime Software or in the Intel Quartus Prime settings file, (.qsf). CONF_DONE and
INIT_DONE are low prior to and during configuration. CONF_DONE asserts when the device finishes receiving configuration
data. INIT_DONE asserts when the device enters user mode.
Note: The entire device does not enter user mode simultaneously.Intel recommends that you include the Reset Release Intel FPGA
IP on page 23 to hold your application logic in the reset state until the entire FPGA fabric is in user mode.
6. Intel Agilex Debugging Guide
UG-20205 | 2019.10.09
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Intel
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Configuration User Guide
189

Intel Agilex Specifications

General

Brand	Intel
Model	Agilex
Category	Microcontrollers
Language	English

Summary

Intel Agilex Configuration User Guide

Intel Agilex Configuration Overview

Provides a general overview of the device's configuration capabilities and security features.

Intel Download Cables Supporting Configuration in Intel Agilex Devices

Details the specific cables used for programming and debugging the device.

Intel Agilex Configuration Details

Intel Agilex Configuration Timing Diagram

Illustrates the critical timing signals and states during configuration and reconfiguration processes.

Configuration Flow Diagram

Visually represents the sequence of states during device configuration.

Reset Release Intel FPGA IP

Explains the IP required to hold designs in reset until configuration is complete.

Additional Clock Requirements for HPS, PCIe, and HBM2

Outlines clock requirements for specific hardware blocks.

Intel Agilex Configuration Pins

Describes the various pins used for configuration and their functions.

SDM Pin Mapping

Details the specific assignments of SDM I/O pins for different configuration schemes.

MSEL Settings

Explains how MSEL pins are used to select the configuration scheme.

Device Configuration Pins for Optional Configuration Signals

Covers configuration pins that are not dedicated and can be assigned optionally.

Specifying Optional Configuration Pins

Provides steps to assign optional configuration pins using software.

Enabling Dual-Purpose Pins

Describes how to enable and configure dual-purpose pins for specific functions.

Configuration Pins I/O Standard, Drive Strength, and IBIS Model

Details electrical characteristics of configuration pins.

Intel Agilex Configuration Schemes

Avalon-ST Configuration

Describes the fastest configuration scheme using Avalon Streaming.

Avalon-ST Configuration Scheme Hardware Components and File Types

Details the components and file types for Avalon-ST configuration.

Enabling Avalon-ST Device Configuration

Steps to enable the Avalon-ST scheme in software.

The AVST_READY Signal

Explains the flow control signal for Avalon-ST.

Debugging Guidelines for the Avalon-ST Configuration Scheme

Offers troubleshooting tips for Avalon-ST configuration issues.

AS Configuration

Describes the Active Serial configuration scheme.

AS Configuration Scheme Hardware Components and File Types

Details hardware components and file types for AS configuration.

AS Single-Device Configuration

Shows connections for single-device AS configuration.

AS Configuration Timing Parameters

Covers timing parameters for AS configuration, including serial output and input diagrams.

Debugging Guidelines for the AS Configuration Scheme

Offers troubleshooting tips for AS configuration.

SD/MMC Configuration

Describes configuration using SD memory cards or MMC.

JTAG Configuration

Explains the simplest device configuration scheme using JTAG.

JTAG Configuration Scheme Hardware Components and File Types

Details hardware components and file types for JTAG configuration.

JTAG Device Configuration

Explains how to configure a single device in a JTAG chain.

Debugging Guidelines for the JTAG Configuration Scheme

Provides troubleshooting tips for JTAG configuration.

IP for Use with the Avalon-ST Configuration Scheme: Intel FPGA Parallel Flash Loader II IP Core

Details the PFL II IP core for Avalon-ST configuration.

Remote System Update (RSU)

Remote System Update Functional Description

Provides an overview of the RSU functionality and its advantages.

RSU Glossary

Defines key terms related to RSU.

Remote System Update Using AS Configuration

Explains how RSU works with the AS configuration scheme.

Remote System Update Configuration Images

Describes the types of images used in RSU.

Remote System Update Configuration Sequence

Illustrates the sequence of operations for RSU.

RSU Recovery from Corrupted Images

Details how to recover from corrupted images during RSU.

Guidelines for Performing Remote System Update Functions for Non-HPS

Provides guidelines for implementing RSU without HPS.

Commands and Responses

Describes the commands and responses used for RSU operations.

Operation Commands

Lists and describes the specific commands for RSU.

Quad SPI Flash Layout

Describes the layout of Quad SPI flash memory for RSU.

High Level Flash Layout

Provides a high-level view of the flash layout.

Standard (non-RSU) Flash Layout

Describes the flash layout for non-RSU scenarios.

RSU Flash Layout – SDM Perspective

Explains the flash layout from the SDM's perspective.

RSU Flash Layout – Your Perspective

Explains the flash layout from the user's perspective.

Detailed Quad SPI Flash Layout

Provides a detailed breakdown of the Quad SPI flash layout.

RSU Sub-Partitions Layout

Details the layout of RSU flash sub-partitions.

Configuration Pointer Block Layout

Explains the structure of the configuration pointer block.

Generating Remote System Update Image Files Using the Programming File Generator

Guides on creating RSU image files.

Generating the Initial RSU Image

Steps to generate the initial RSU image.

Generating an Application Image

Steps to generate an application image.

Generating a Factory Update Image

Steps to generate a factory update image.

Programming Flash Memory with the Initial Remote System Update Image

Details programming the flash with the initial RSU image.

Reconfiguring the Device with an Application or Factory Image

Explains how to reconfigure the device with different images.

Adding an Application Image

Steps to add a new application image.

Intel Agilex Configuration Features

Device Security

Covers the security features of Intel Agilex devices.

Configuration via Protocol

Explains the CvP configuration scheme.

Partial Reconfiguration

Describes the process of reconfiguring parts of the FPGA.

Intel Agilex Debugging Guide

Configuration Debugging Checklist

A checklist to help identify and resolve configuration issues.

Intel Agilex Configuration Architecture Overview

Provides an overview of the device's configuration architecture.

Configuration File Format Differences

Explains differences in configuration file formats.

Understanding and Troubleshooting Configuration Pin Behavior

Explains the behavior of configuration pins and how to troubleshoot them.

nCONFIG

Details the function and behavior of the nCONFIG pin.

nSTATUS

Details the function and behavior of the nSTATUS pin.

CONF_DONE and INIT_DONE

Describes the CONF_DONE and INIT_DONE signals.

Intel Agilex Configuration User Guide Archives

IP Core Version User Guide

Lists user guides for different IP core versions.

Document Revision History for the Intel Agilex Configuration User Guide

Changes

Details the changes made in different document versions.