Contents
1. Intel
®
Agilex
™
Configuration User Guide................................................................................................................................ 5
1.1. Intel
®
Agilex
™
Configuration Overview.............................................................................................................................5
1.1.1. Configuration and Related Signals.......................................................................................................................8
1.1.2. Intel Download Cables Supporting Configuration in Intel Agilex Devices................................................................... 9
1.2. Intel Agilex Configuration Architecture...........................................................................................................................11
1.2.1. Secure Device Manager................................................................................................................................... 12
2. Intel Agilex Configuration Details........................................................................................................................................ 16
2.1. Intel Agilex Configuration Timing Diagram......................................................................................................................16
2.2. Configuration Flow Diagram......................................................................................................................................... 20
2.3. Reset Release Intel FPGA IP......................................................................................................................................... 23
2.4. Additional Clock Requirements for HPS, PCIe, and HBM2................................................................................................. 25
2.5. Intel Agilex Configuration Pins...................................................................................................................................... 25
2.5.1. SDM Pin Mapping............................................................................................................................................ 26
2.5.2. MSEL Settings................................................................................................................................................ 27
2.5.3. Device Configuration Pins for Optional Configuration Signals................................................................................. 28
2.6. Configuration Clocks....................................................................................................................................................38
2.6.1. Setting Configuration Clock Source....................................................................................................................38
2.6.2. OSC_CLK_1 Clock Input...................................................................................................................................39
3. Intel Agilex Configuration Schemes..................................................................................................................................... 41
3.1. Avalon-ST Configuration.............................................................................................................................................. 41
3.1.1. Avalon-ST Configuration Scheme Hardware Components and File Types ................................................................ 43
3.1.2. Enabling Avalon-ST Device Configuration............................................................................................................44
3.1.3. The AVST_READY Signal ................................................................................................................................. 45
3.1.4. RBF Configuration File Format...........................................................................................................................48
3.1.5. Avalon-ST Single-Device Configuration...............................................................................................................49
3.1.6. Debugging Guidelines for the Avalon-ST Configuration Scheme............................................................................. 52
3.1.7. QSF Assignments for Avalon-ST x8....................................................................................................................53
3.1.8. QSF Assignments for Avalon-ST x16.................................................................................................................. 55
3.1.9. QSF Assignments for Avalon-ST x32.................................................................................................................. 57
3.1.10. IP for Use with the Avalon-ST Configuration Scheme: Intel FPGA Parallel Flash Loader II IP Core............................. 59
Contents
Intel
®
Agilex
™
Configuration User Guide
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