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Figure 7.
Reset Release Intel FPGA IP INIT_DONE External Connection
If you do not include the R
eset Release Intel FPGA IP in your design, you must feed the
INIT_DONE
signal back into your
design as an input to your reset logic as shown in this figure.
Board
INIT_DONE
Reset
Application Logic
Intel FPGA
2. Intel Agilex Configuration Details
UG-20205 | 2019.10.09
Intel
®
Agilex
™
Configuration User Guide
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Table of Contents
Default Chapter
2
Table of Contents
2
1 Intel ® Agilex ™ Configuration User Guide
5
Intel ® Agilex ™ Configuration Overview
5
Configuration and Related Signals
8
Intel Download Cables Supporting Configuration in Intel Agilex Devices
9
Intel Agilex Configuration Architecture
11
Secure Device Manager
12
2 Intel Agilex Configuration Details
16
Intel Agilex Configuration Timing Diagram
16
Configuration Flow Diagram
20
Reset Release Intel FPGA IP
23
Additional Clock Requirements for HPS, Pcie, and HBM2
25
Intel Agilex Configuration Pins
25
SDM Pin Mapping
26
MSEL Settings
27
Device Configuration Pins for Optional Configuration Signals
28
Configuration Clocks
38
Setting Configuration Clock Source
38
OSC_CLK_1 Clock Input
39
3 Intel Agilex Configuration Schemes
41
Avalon-ST Configuration
41
Avalon-ST Configuration Scheme Hardware Components and File Types
43
Enabling Avalon-ST Device Configuration
44
The AVST_READY Signal
45
RBF Configuration File Format
48
Avalon-ST Single-Device Configuration
49
Debugging Guidelines for the Avalon-ST Configuration Scheme
52
QSF Assignments for Avalon-ST X8
53
QSF Assignments for Avalon-ST X16
55
QSF Assignments for Avalon-ST X32
57
IP for Use with the Avalon-ST Configuration Scheme: Intel FPGA Parallel Flash Loader II IP Core
59
AS Configuration
86
AS Configuration Scheme Hardware Components and File Types
88
AS Single-Device Configuration
90
AS Using Multiple Serial Flash Devices
91
AS Configuration Timing Parameters
93
Maximum Allowable External AS_DATA Pin Skew Delay Guidelines
94
Programming Serial Flash Devices
95
Serial Flash Memory Layout
99
As_Clk
100
Active Serial Configuration Software Settings
101
Intel Quartus Prime Programming Steps
102
Debugging Guidelines for the as Configuration Scheme
106
QSF Assignments for as
108
SD/MMC Configuration
111
SD/MMC Single-Device Configuration
112
JTAG Configuration
113
JTAG Configuration Scheme Hardware Components and File Types
114
JTAG Device Configuration
115
JTAG Multi-Device Configuration
118
Debugging Guidelines for the JTAG Configuration Scheme
119
4 Remote System Update (RSU)
121
Remote System Update Functional Description
123
Remote System Update Using as Configuration
124
Remote System Update Configuration Images
125
Remote System Update Configuration Sequence
126
RSU Recovery from Corrupted Images
127
Updates with the Factory Update Image
130
Guidelines for Performing Remote System Update Functions for Non-HPS
131
Commands and Responses
132
Operation Commands
134
Error Code Responses
140
Quad SPI Flash Layout
141
Detailed Quad SPI Flash Layout
146
Generating Remote System Update Image Files Using the Programming File Generator
151
Generating an Application Image
153
Generating a Factory Update Image
155
Remote System Update from FPGA Core Example
159
Creating Initial Flash Image Containing Bitstreams for Factory Image and One Application Image
161
Programming Flash Memory with the Initial Remote System Update Image
167
Reconfiguring the Device with an Application or Factory Image
171
Adding an Application Image
172
Removing an Application Image
177
5 Intel Agilex Configuration Features
180
Partial Reconfiguration
182
6 Intel Agilex Debugging Guide
183
Intel Agilex Configuration Architecture Overview
184
Configuration File Format Differences
185
Understanding Seus
186
Understanding and Troubleshooting Configuration Pin Behavior
187
Nconfig
188
CONF_DONE and INIT_DONE
189
SDM_IO Pins
190
7 Intel Agilex Configuration User Guide Archives
193
8 Document Revision History for the Intel Agilex Configuration User Guide
194
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Intel Agilex Specifications
General
Brand
Intel
Model
Agilex
Category
Microcontrollers
Language
English
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