Intel Agilex

Figure 7. Reset Release Intel FPGA IP INIT_DONE External Connection
If you do not include the Reset Release Intel FPGA IP in your design, you must feed the INIT_DONE signal back into your
design as an input to your reset logic as shown in this figure.
Board
INIT_DONE
Reset
Application Logic
Intel FPGA
2. Intel Agilex Configuration Details
UG-20205 | 2019.10.09
Intel
®
Agilex
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Configuration User Guide
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