Intel Agilex User Manual

Signal Name Pin Type Direction Powered by
MSEL[2:0]
SDM I/O, Dual-Purpose Input V
CCIO_SDM
CONF_DONE
(5)
SDM I/O Output V
CCIO_SDM
AVSTx8_READY
SDM I/O Output V
CCIO_SDM
AVST_READY
GPIO, Dual-Purpose Output V
CCIO
AVSTx8_DATA[7:0]
SDM I/O Input V
CCIO_SDM
AVSTx8_VALID
SDM I/O Input V
CCIO_SDM
AVSTx8_CLK
SDM I/O Input V
CCIO_SDM
AVST_DATA[31:0]
GPIO, Dual-Purpose Input V
CCIO
AVST_VALID
GPIO, Dual-Purpose Input V
CCIO
AVST_CLK
GPIO, Dual-Purpose Input V
CCIO
Refer to the Intel Agilex Data Sheet for configuration timing estimates.
The x16 and x32 modes use GPIO pins that only support the 1.2 V I/O standard. The SDM I/O pins require a 1.8 V power
supply. Consequently, you may need a voltage-level translation between the FPGA and external host because some signals, to
accommodate both power requirements.
Note:
Although the INIT_DONE configuration signal is not required for configuration, Intel recommends that you use this signals.
The SDM drives the INIT_DONE signal high to indicate the device is fully in user mode. This signal is important when
debugging configuration.
Note: If you create custom logic instead of using the PFL II IP to drive configuration, refer to the Avalon Streaming Interfaces in the
Avalon Interface Specifications for protocol details.
Related Information
• Avalon Interface Specifications
• Intel Agilex Device Data Sheet
(5)
CONF_DONE is required if you are using the Intel FPGA Parallel Flash Loader II IP as the configuration host.
3. Intel Agilex Configuration Schemes
UG-20205 | 2019.10.09
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Intel Agilex Specifications

General

Brand	Intel
Model	Agilex
Category	Microcontrollers
Language	English