3 Remote Interface Reference
SCPI Status Registers
114 E364xA User’s and Service Guide
Status byte register
The Status Byte summary register reports conditions from
the other status registers. Query data that is waiting in the
power supply’s output buffer is immediately reported
through the “Message Available” bit (bit 4) of the Status Byte
register. Bits in the summary register are not latched.
Clearing an event register will clear the corresponding bits
in the Status Byte summary register. Reading all messages in
the output buffer, including any pending queries, will clear
the message available bit.
The Status Byte summary register is cleared when you
execute the *CLS (clear status) command.
Querying the Standard Event register (*ESR? command) will
clear only bit 5 in the Status Byte summary register.
For example, 24 (8 + 16) is returned when you have queried
the status of the Status Byte register, QUES and MAV
conditions have occurred.
Table 3 - 6 Bit definitions — Status Byte summary register
Bit Decimal value Definition
0-2 Not Used 0 Always set to 0.
3 QUES 8 One or more bits are set in the Questionable Status register (bits must
be enabled in the enable register).
4 MAV 16 Data is available in the power supply output buffer.
5 ESB 32 One or more bits are set in the Standard Event register (bits must be
enabled in the enable register).
6 RQS 64 The power supply is requesting service (serial poll).
7 Not Used 0 Always set to 0.
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