Keysight E4990A - Page 332

E4990A Help
322
Status Bit Definitions of the Questionable Limit Status Condition
Register
Bit
Position
Name Description
0 Not used Always 0
1
Channel 1 Limit Test Fail
(questionable limit
channel 1 status register
summary)
Set to "1" while one of the
enabled bits in the
questionable limit channel 1
status event register is set to
"1."
2
Channel 2 Limit Test Fail
(questionable limit
channel 2 status register
summary)
Set to "1" while one of the
enabled bits in the
questionable limit channel 2
status event register is set to
"1."
3
Channel 3 Limit Test Fail
(questionable limit
channel 3 status register
summary)
Set to "1" while one of the
enabled bits in the
questionable limit channel 3
status event register is set to
"1."
4
Channel 4 Limit Test Fail
(questionable limit
channel 4 status register
Set to "1" while one of the
enabled bits in the
questionable limit channel 4
status event register is set to