Configuration
Function blocks
Master frequency processing (DFSET)
8
8.2
8.2.5
8.2−19
EDSVF9383V EN 7.1−04/2012
IMPORTANTPossible settingsCode
SelectionLenzeNameNo.
C0520
CFG: IN 1000 FIXEDPHI−0 Selection list 4 Configuration of input signal,
function block DFSET
l Input of speed / phase setpoint
signal
8.2−18
C0521
CFG: VP−DIV 1000 FIXED0% Selection list 1 Configuration of analog input
signal, function block DFSET
l Signal for numerator of
stretching factor
l 100 % = 16384 inc
C0522
CFG: RAT−DIV 1000 FIXED0% Selection list 1 Configuration of analog input
signal, function block DFSET
l Signal for numerator of
gearbox factor
l 100 % = 16384 inc
C0523
CFG: A−TRIM 1000 FIXED0% Selection list 1 Configuration of analog input
signal, function block DFSET
l Signal for phase trimming via
offset multiplier (C0529)
l 100 % = 16384 inc
C0524
CFG: N−TRIM 1000 FIXED0% Selection list 1 Configuration of analog input
signal, function block DFSET
l Signal for speed trimming
l Signal in [%] of C0011
C0525
CFG: 0−PULSE 1000 FIXED0 Selection list 2 Configuration of digital input
signal, function block DFSET
l Signal for one−time zero pulse
activation
l HIGH = release for zero pulse
synchronisation
C0526
CFG: RESET 1000 FIXED0 Selection list 2 Configuration of digital input
signal, function block DFSET
l Signal for reset of integrators
l HIGH sets
– Position difference = 0
– DFSET−PSET = 0
– DFSET−PSET2 = 0
C0527
CFG: SET 1000 FIXED0 Selection list 2 Configuration of digital input
signal, function block DFSET
l HIGH = Set phase integrators
to equal values
l LOW−HIGH edge sets
DFSET−PSET = 0
l HIGH−LOW edge sets
DFSET−PSET to the current
value of MCTRL−PHI−SET
l DFSET−SET has a higher priority
than DFSET−RESET
C0528 −2
.
10
9
{1} 2
.
10
9
Function block DFSET
l Display only
8.2−18
1 DIS: 0−pulse A Phase difference between two
zero pulses
2 DIS: Offset Offset = C0523 × C0529 + C0252
To Next Page
Loading...
Need help?
General
