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13-2-7. Equivalent circuit of input/output
13-2-8. Timing chart
(1) Normal
(2) When the data is over
●At the time of data output of each P.C., DATA and POL., output transistor will become ON(Negative logic electrically).
● At the time of OVR output, output transistor will at the OVER signal will become ON(Negative logic electrically). Moreover, for all of the
output transistor will become OFF (Positive logic electrically) at the time of OVER output. (However, for the POL., normal OFF at the “OL”,
DATA, and normal ON at the “－OL”).
DATA
POL.
P.C.
ON
ON
ONON
ON
ON
ON
ON
5 times/s：Approx.125 ms/ Approx.25 ms changeable
15 times/s：Approx.25 ms
5 times/s：Approx.200 ms
15 times/s：Approx.66 ms
DATA
POL.
P.C.
OVER
ON
ON
ON ONON ON
Input section
Output section
ON
V
CE
＝DC30 V
I
C
＝DC20 mA MAX
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