Phytec phyFLEX-i.MX 6 - Page 28

phyFLEX
®
-i.MX 6 [PFL-A-XL1-xxx
12  PHYTEC Messtechnik GmbH 2013 L-773e_2
X1A30
X_SPI1_CS0
1
O VDD_3V3_LOGIC SPI1 chip select 0
X1A31 X_SPI1_MOSI
1
O VDD_3V3_LOGIC
SPI1 master output/slave
input
X1A32 X_SPI1_MISO
1
I VDD_3V3_LOGIC
SPI1 master input/slave
output
X1A33 reference-voltage REF_O VDD_3V3_LOGIC SPI1 reference voltage
X1A34 GND - - Ground 0 V
X1A35 X_SPI1_CLK
1
O VDD_3V3_LOGIC SPI1 clock signal
X1A36 X_SPI1_CS1
1
O VDD_3V3_LOGIC SPI1 chip select 1
X1A37 X_USB0_nVBUSEN O VDD_3V3_LOGIC
USB0 VBUS enable
(active low)
X1A38 X_USB0_VBUS PWR_I 5V USB0 VBUS input
X1A39 X_USB0_nOC IPU VDD_3V3_LOGIC USB0 overcurrent input
X1A40 GND - - Ground 0 V
X1A41 reference-voltage REF_O VDD_3V3_LOGIC USB0 reference voltage
X1A42 X_USB0_CHGDET O VDD_3V3_LOGIC USB0 charger detection
X1A43 X_USB1_nVBUSEN O VDD_3V3_LOGIC
USB1 VBUS enable
(active low)
X1A44 X_USB1_VBUS PWR_I 5V USB1 VBUS input
X1A45 X_USB1_nOC IPU VDD_3V3_LOGIC USB1 overcurrent input
X1A46 GND - - Ground 0 V
X1A47 reference-voltage REF_O VDD_3V3_LOGIC USB1 reference voltage
X1A48 X_I2S0_CLK O VDD_3V3_LOGIC I
2
S receive clock
X1A49 X_I2S0_FRM O VDD_3V3_LOGIC I
2
S receive frame
X1A50 X_I2S0_ADC I VDD_3V3_LOGIC I
2
S receive data
X1A51 reference-voltage REF_O VDD_3V3_LOGIC I
2
S reference voltage
X1A52 GND - - Ground 0 V
X1A53 X_I2S0_DAC O VDD_3V3_LOGIC I
2
S transmit data
X1A54 X_GPIO0 I/O VDD_3V3_LOGIC
General purpose
input/output 0
X1A55 X_GPIO1 I/O VDD_3V3_LOGIC
General purpose
input/output 1
X1A56 X_GPIO2 I/O VDD_3V3_LOGIC
General purpose
input/output 2
X1A57 reference-voltage REF_O VDD_3V3_LOGIC GPIO reference voltage
X1A58 GND - - Ground 0 V
X1A59 X_GPIO3 I/O VDD_3V3_LOGIC
General purpose
input/output 3
X1A60 X_GPIO4 I/O VDD_3V3_LOGIC
General purpose
input/output 4
Table 3: Pinout of the phyFLEX-fix Connector X1, Row A (continued)
1
: SPI1 is not available for i.MX 6 Solo and i.MX 6 Dual Lite
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