Phytec phyFLEX-i.MX 6 - LVDS Display Signals (Connector X3)

LVDS Display Interface
 PHYTEC Messtechnik GmbH 2013 L-773e_2
63
Furthermore the phyFLEX-i.MX 6 supports a second LVDS Display
at the non standardized phyFLEX-flex connector X3. The table below
shows the location of the signals:
Pin # Signal ST Voltage Domain Description
X3B1 X_LVDS1_TX0_P LVDS_O i.MX 6 internal
LVDS1
data0+
X3B2 X_LVDS1_TX0_N LVDS_O i.MX 6 internal
LVDS1
data0-
X3B4 X_LVDS1_TX1_P LVDS_O i.MX 6 internal
LVDS1
data1+
X3B5 X_LVDS1_TX1_N LVDS_O i.MX 6 internal
LVDS1
data1-
X3B7 X_LVDS1_TX2_P LVDS_O i.MX 6 internal
LVDS1
data2+
X3B8 X_LVDS1_TX2_N LVDS_O i.MX 6 internal
LVDS1
data2-
X3B10 X_LVDS1_TX3_P LVDS_O i.MX 6 internal
LVDS1
data3+
X3B11 X_LVDS1_TX3_N LVDS_O i.MX 6 internal
LVDS1
data3-
X3B13 X_LVDS1_CLK_P LVDS_O i.MX 6 internal
LVDS1
clock+
X3B14 X_LVDS1_CLK_N LVDS_O i.MX 6 internal
LVDS1
cloc
k
-
Table 31: Second Display Interface Signal Location at X3
12.1 LVDS Display Interface pixel mapping
The phyFLEX specification defines the pixel mapping of the LVDS
display interface. The pixel mapping equates to the OpenLDI
respectively Intel 24.0 or JEIDA standard. Thus you can connect 18-
bit as well as 24-bit LVDS displays to the phyFLEX. Table 32 and
Table 33 show the recommended pixel mapping of the LVDS display.
However since the i.MX 6 LDB Module supports also the SPWG
pixel mapping, this one can be used as well by setting the appropriated
configuration bit.
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