Phytec phyFLEX-i.MX 6 - phyFLEX-fix Connector X1 Pinout (Row A)

Pin Description
 PHYTEC Messtechnik GmbH 2013 L-773e_2
11
Pin # Signal ST Voltage domain Description
X1A1 VDD_5V_IN_R PWR_I 5V
5 V Primary Voltage
Supply Input
X1A2 VDD_5V_IN_R PWR_I 5V
5 V Primary Voltage
Supply Input
X1A3 VDD_5V_IN_R PWR_I 5V
5 V Primary Voltage
Supply Input
X1A4 GND - - Ground 0 V
X1A5 X_JTAG_TRSTB I VDD_3V3_LOGIC
JTAG reset input (low
active)
X1A6 X_JTAG_TDI I VDD_3V3_LOGIC JTAG TDI
X1A7 X_JTAG_TMS I VDD_3V3_LOGIC JTAG TMS
X1A8 X_JTAG_TDO O VDD_3V3_LOGIC JTAG TDO
X1A9 X_JTAG_TCK I VDD_3V3_LOGIC JTAG clock input
X1A10 GND - - Ground 0 V
X1A11 N.C. - - Not connected
X1A12 X_UART1_TxD_TTL O VDD_3V3_LOGIC
UART1 serial transmit
signal
X1A13 X_UART1_RxD_TTL I VDD_3V3_LOGIC
UART1 serial data receive
signal
X1A14 X_UART1_RTS_TTL O VDD_3V3_LOGIC UART1 request to send
X1A15 X_UART1_CTS_TTL I VDD_3V3_LOGIC UART1 clear to send
X1A16 GND - - Ground 0 V
X1A17 reference-voltage REF_O VDD_3V3_LOGIC UART1 reference voltage
X1A18 X_UART0_TxD_TTL O VDD_3V3_LOGIC
UART0 serial transmit
signal
X1A19 reference-voltage REF_O VDD_3V3_LOGIC UART0 reference voltage
X1A20 X_UART0_RxD_TTL I VDD_3V3_LOGIC
UART0 serial data receive
signal
X1A21 X_SPI0_MOSI O VDD_3V3_LOGIC
SPI0 master output/slave
input
X1A22 GND - - Ground 0 V
X1A23 X_SPI0_MISO I VDD_3V3_LOGIC
SPI0 master input/slave
output
X1A24 X_SPI0_CSBOOT O VDD_3V3_LOGIC SPI0 Chip Select BOOT
X1A25 X_SPI0_CS0 O VDD_3V3_LOGIC SPI0 Chip Select 0
X1A26 X_SPI0_CS1 O VDD_3V3_LOGIC SPI0 Chip Select 1
X1A27 reference-voltage REF_O VDD_3V3_LOGIC SPI0 reference voltage
X1A28 GND - - Ground 0 V
X1A29 X_SPI0_CLK O VDD_3V3_LOGIC SPI0 clock signal
Table 3: Pinout of the phyFLEX-fix Connector X1, Row A
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