Phytec phyFLEX-i.MX 6 - Block Diagram of the System

phyFLEX
®
-i.MX 6 [PFL-A-XL1-xxx
4  PHYTEC Messtechnik GmbH 2013 L-773e_2
1.1 Block Diagram
Figure 1: Block Diagram of the phyFLEX-i.MX 6
i.MX 6
DDR3 (64Bit)
Bank1
DDR3 (64Bit)
Bank2
PMIC
NAND-Flash
SPI-NOR-Flash
phyFLEX-fix (X1)
and
phyFLEX-optional
(X2) Connector
USB_OTG, USB_H1 (both i.MX6 internal PHY)
Display LVDS0 (4 lanes + clock)
HDMI
I2S (1 output lanes, 1 input lane)
Ethernet PHY
RGMII
10/100/1000 MBit Ethernet
PCIe
SAT
A
2 x UART
CAN
2 x SD-Interface (8 bit, 4 bit)
2 x SPI (1 with 4 CS, 1 with 1 CS)
2 x I2C
9 GPIOs
JTAG
phyFLEX-flex (X3)
Connector
Display LVDS1
MLB
CSI 1 parallel Camera, GPIOs
CSI0 Camera parallel
LVDS Converter
Camera0 LVDS
DISP0 parallel Display Inteface and Address/Databus,
multiplexed with other functions at connector X1 or X2
I2C EEPROM
EMIC
I2C1
Control Signals
Control Signals
(Reset, Wake-up, Bootpins)
LVDS Converter
Camera1 LVDSCSI1 Camera parallel
CMIC
FAN control, PM-Bus (I2C)
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