Phytec phyFLEX-i.MX 6 - SD; MMC Card Interfaces; SD;MMC Interface Signal Locations

SD / MMC Card Interfaces
 PHYTEC Messtechnik GmbH 2013 L-773e_2
41
7 SD / MMC Card Interfaces
The phyFLEX bus features one fixed and one optional SD / MMC
Card interface. On the phyFLEX-i.MX 6 the interface signals extend
from the controllers third and second Ultra Secured Digital (uSDHC3
/ uSDHC2) Host Controller to the phyFLEX-Connector. Table 15
shows the location of the different interface signals on the phyFLEX-
Connector. The MMC/SD/SDIO Host Controller is fully compatible
with the SD Memory Card Specification 3.0 and SD I/O Specification,
Part E1, v1.10. SD / MMC Card interface SD0 (uSDHC3 of the
i.MX 6), supports 8 data channels and SD1 (uSDHC2 of the i.MX 6) 4
data channels. Both interfaces have a maximum data rate of up to
104 MB/s (refer to the i.MX 6 Reference Manual for more
information).
Pin # Signal ST
Voltage
Domain
Description
X1B8 reference-voltage REF_O VDD_SD0
SD0 reference
voltage
X1B9 X_SD0_nWP I VDD_SD0
SD0 write protect-
tion (active low)
X1B10 X_SD0_nCD I VDD_SD0
SD0 card detection
(active low)
X1B11 X_SD0_D3 I/O VDD_SD0 SD0 data 3
X1B12 X_SD0_CMD O VDD_SD0 SD0 command
X1B13 GND - - Ground 0 V
X1B14 X_SD0_CLK O VDD_SD0 SD0 clock
X1B15 X_SD0_D0 I/O VDD_SD0 SD0 data 0
X1B16 X_SD0_D1 I/O VDD_SD0 SD0 data 1
X1B17 X_SD0_D2 I/O VDD_SD0 SD0 data 2
X1B18 X_SD0_D4 I/O VDD_SD0 SD0 data 4
X1B20 X_SD0_D5 I/O VDD_SD0 SD0 data 5
X1B21 X_SD0_D6 I/O VDD_SD0 SD0 data 6
Table 15: Location of SD/ MMC Card Interface Signals
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