Phytec phyFLEX-i.MX 6 - LVDS Display Interface; LVDS Display Signal Locations (Connector X1)

phyFLEX
®
-i.MX 6 [PFL-A-XL1-xxx
62  PHYTEC Messtechnik GmbH 2013 L-773e_2
12 LVDS Display Interface
The LVDS-Signals from the on-chip LVDS Display Bridge (LDB) of
the i.MX 6 are brought out at the phyFLEX-fix connector X1. Thus an
LVDS-Display can connect directly to the phyFLEX-i.MX 6. The
location of the applicable interface signals (X_LVDS0_L0-3+,
X_LVDS0_L0-3-, X_LVDS0_CLK+ and X_LVDS0_CLK-) and of
the two control signals display enable and backlight PWM
(nLVDS0_DISP_EN and LVDS0_DISP_BL_PWM) can be found in
the table below.
Pin # Signal ST Voltage Domain Description
X1B50 X_LVDS0_L0+ LVDS_O i.MX 6 internal
LVDS0
data0+
X1B51 X_LVDS0_L0- LVDS_O i.MX 6 internal LVDS0 data0-
X1B52 X_LVDS0_nDISP_EN O VDD_3V3_LOGIC
LVDS0
display enable
(low active)
X1B53 X_LVDS0_L1+ LVDS_O i.MX 6 internal
LVDS0
data1+
X1B54 X_LVDS0_L1- LVDS_O i.MX 6 internal LVDS0 data1-
X1B56 X_LVDS0_L2+ LVDS_O i.MX 6 internal
LVDS0
data2+
X1B57 X_LVDS0_L2- LVDS_O i.MX 6 internal LVDS0 data2-
X1B58
X_LVDS0_DISP_BL_
PWM
O VDD_3V3_LOGIC
LVDS0
backlight
PWM output
X1B59 X_LVDS0_L3+ LVDS_O i.MX 6 internal
LVDS0
data3+
X1B60 X_LVDS0_L3- LVDS_O i.MX 6 internal LVDS0 data3-
X1B62 X_LVDS0_CLK+ LVDS_O i.MX 6 internal
LVDS0
clock+
X1B63 X_LVDS0_CLK- LVDS_O i.MX 6 internal LVDS0 clock-
X1B64 reference-voltage REF_O VDD_3V3_LOGIC
LVDS0
reference
voltage
Table 30: Display Interface Signal Location
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