Phytec phyFLEX-i.MX 6 - LVDS Camera Interface; LVDS Camera Signal Locations (Connector X2)

phyFLEX
®
-i.MX 6 [PFL-A-XL1-xxx
66  PHYTEC Messtechnik GmbH 2013 L-773e_2
14 LVDS Camera Interface
The phyFLEX-i.MX 6 uses two 1-channel 10-Bit LVDS Random
Lock Deserializer (U12 and U27) to receive LVDS-Signals from a
LVDS Camera Interface. The LVDS Deserializer converts the LVDS
Signals to a 10-bit wide parallel data bus and separate clock which can
be used as inputs for the i.MX 6 Camera Sensor Interfaces (U12 is
connected to CSI1 and U27 is connected to CSI0). The 10-bit wide
data bus consists of 8 color information bits and 2 sync bits
(HSYNC/VSYNC).
The following table shows the location of the applicable
interface signals (X_CAMERAx_CLK, X_CAMERAx_L+,
X_CAMERAx_L-) on the phyFLEX-Connector.
Pin # Signal ST Voltage Domain Description
X2A40 X_CAMERA0_L0+ LVDS_I VDD_3V3_LOGIC Camera0 data+
X2A41 X_CAMERA0_L0- LVDS_I VDD_3V3_LOGIC Camera0 data-
X2A43 X_CAMERA0_CLK O VDD_3V3_LOGIC
Camera0
master clock
X2A44 reference-voltage REF_O VDD_3V3_LOGIC
Camera0 refe-
rence voltage
X2A46 X_CAMERA1_L0+ LVDS_I VDD_3V3_LOGIC Camera1 data+
X2A47 X_CAMERA1_L0- LVDS_I VDD_3V3_LOGIC Camera1 data-
X2A49 X_CAMERA1_CLK O VDD_3V3_LOGIC
Camera1
master clock
X2A50 reference-voltage REF_O VDD_3V3_LOGIC
Camera1 refe-
rence voltage
Table 35: Camera Interface Signal Location at X2
To assists the implementation of a power management the
Deserializer’s REN inputs are connected to the CSI0_DATA_EN pad
(U27) respectively to the EIM_DA10 pad (U12) of the i.MX 6.
Furthermore the nPWRDN signals of the Deserializers are connected
to the ENET_RX_ER pad (U27) respectively to the EIM_EB0 pad
(U12) of the i.MX 6. Thereby the LVDS Deserializer can be turned
off by software.
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