Phytec phyFLEX-i.MX 6 - High-Definition Multimedia Interface (HDMI); HDMI Interface Signal Locations (Connector X2)

LVDS Display Interface
 PHYTEC Messtechnik GmbH 2013 L-773e_2
65
13 High-Definition Multimedia Interface (HDMI)
The High-Definition Multimedia Interface (HDMI) of the
phyFLEX-i.MX 6 is compliant to HDMI 1.4 and DVI 1.0. It supports
a maximum pixel clock of up to 340 MHz for up to 720p at 100 Hz
and 720i at 200 Hz, or 1080p at 60 Hz and 1080i/720i at 120 Hz
HDTV display resolutions, and a graphic display resolution of up to
2048x1536 (QXGA). Please refer to the i.MX 6 Reference Manual for
more information.
The following table shows the location of the HDMI signals on the
phyFLEX-optional connector X2.
Pin # Signal ST Voltage Domain Description
X2A8 X_HDMI0_SDA I/O VDD_3V3_LOGIC
HDMI0 I2C
data
X2A9 X_HDMI0_SCL I/O VDD_3V3_LOGIC
HDMI0 I2C
clock
X2B1 X_HDMI0_TMDS_DATA2+ TMDS_O i.MX 6 internal
HDMI0
data2+
X2B2 X_HDMI0_TMDS_DATA2- TMDS_O i.MX 6 internal
HDMI0
data2-
X2B4 X_HDMI0_TMDS_DATA1+ TMDS_O i.MX 6 internal
HDMI0
data1+
X2B5 X_HDMI0_TMDS_DATA1- TMDS_O i.MX 6 internal
HDMI0
data1-
X2B6 reference-voltage REF_O VDD_3V3_LOGIC
HDMI0
reference
voltage
X2B7 X_HDMI0_TMDS_DATA0+ TMDS_O i.MX 6 internal
HDMI0
data0+
X2B8 X_HDMI0_TMDS_DATA0- TMDS_O i.MX 6 internal
HDMI0
data0-
X2B10 X_HDMI0_TMDS_CLOCK+ TMDS_O i.MX 6 internal
HDMI0
clock+
X2B11 X_HDMI0_TMDS_CLOCK- TMDS_O i.MX 6 internal
HDMI0
clock-
X2B12 X_HDMI0_CEC I/O VDD_3V3_LOGIC
HDMI0
CEC
X2B13 X_HDMI0_nHPD I VDD_3V3_LOGIC
HDMI0 hot
plug detect
Table 34: HDMI Interface Signal Location at X2
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