Phytec phyFLEX-i.MX 6 - Debug Interface (JTAG); JTAG Interface Signal Location (Connector X1)

phyFLEX
®
-i.MX 6 [PFL-A-XL1-xxx
58  PHYTEC Messtechnik GmbH 2013 L-773e_2
11 Debug Interface (X1, X4)
The phyFLEX-i.MX 6 is equipped with a JTAG interface for
downloading program code into the external flash, internal controller
RAM or for debugging programs currently executing. The JTAG
interface extends to the phyFLEX-fix connector X1 and also to a
2.0 mm pitch pin header at X4 on the edge of the module PCB.
Table 28 shows the location of the JTAG pins on the phyFLEX-fix
connector X1.
Pin # Signal ST Voltage Domain Description
X1A5 X_JTAG_nTRST I VDD_3V3_LOGIC
JTAG reset
input
X1A6 X_JTAG_TDI I VDD_3V3_LOGIC JTAG TDI
X1A7 X_JTAG_TMS I VDD_3V3_LOGIC JTAG TMS
X1A8 X_JTAG_TDO O VDD_3V3_LOGIC JTAG TDO
X1A9 X_JTAG_TCK I VDD_3V3_LOGIC
JTAG clock
input
X1A10 GND - - Ground 0 V
X1A11 X_JTAG_RTCLK O VDD_3V3_LOGIC
JTAG
RTCLK
X1B5 reference-voltage REF_O VDD_3V3_LOGIC
JTAG
reference
voltage
Table 28: Debug Interface Signal Location at phyFLEX-Connector X1
Figure 9 and Figure 10 show the position of the debug interface
(JTAG connector X4) on the phyFLEX-i.MX 6 module.
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