Phytec phyFLEX-i.MX 6 - System Memory; DDR3-SDRAM Details

phyFLEX
®
-i.MX 6 [PFL-A-XL1-xxx
38  PHYTEC Messtechnik GmbH 2013 L-773e_2
6 System Memory
The phyFLEX-i.MX 6 provides three types of on-board memory:
 2 Banks DDR3 RAM: 1 GB DDR3 SDRAM (up to 4 GB)
4
 NAND Flash (VFBGA): 1 GB (up to 16 GB)
1
 I²C-EEPROM: 4 kB
1
 SPI Flash: 16 MB
1
The following sections of this chapter detail each memory type used
on the phyFLEX-i.MX 6.
6.1 DDR3-SDRAM (U2-U9)
The RAM memory of the phyFLEX-i.MX 6 is comprised of up to two
64 bit wide banks each of four 16-bit wide DDR3-SDRAM chips
(Bank 1: U2-U5, Bank 2: U6-U9). The chips are connected to the
special DRR interface called Multi Mode DDR Controller (MMDC)
of the i.MX 6 processor.
The DDR3 memory is accessed via the second AHB port starting at
0x1000 0000.
Typically the DDR3-SDRAM initialization is performed by a boot
loader or operating system following a power-on reset and must not be
changed at a later point by any application code. When writing custom
code independent of an operating system or boot loader, SDRAM
must be initialized by accessing the appropriate SDRAM
configuration registers on the i.MX 6 controller. Refer to the i.MX 6
Reference Manual for accessing and configuring these registers.
4
: Please contact PHYTEC for more information about additional module configurations.
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