Phytec phyFLEX-i.MX 6 - PCI Express Interface

Serial Interfaces
 PHYTEC Messtechnik GmbH 2013 L-773e_2
53
8.10 PCI Express Interface
The 1-lane PCI Express interface of the phyFLEX-i.MX 6 provides
PCIe Gen. 2.0 functionality which supports 5 Gbit/s operation.
Furthermore the interface is fully backwards compatible to the
2.5 Gbit/s Gen. 1.1 specification. The present and the wake signals are
realized by GPIOs.
Table 25 shows the position of the PCIe signals on the phyFLEX-fix
connector X1.
Pin # Signal ST Voltage Domain Description
X1B65 X_PCIe0_nPRSNT I/O VDD_3V3_LOGIC
PCIe0 present
signal (low active)
X1B66 reference-voltage REF_O VDD_3V3_LOGIC
PCIe0 reference
voltage
X1B68 X_PCIe0_TX+ PCIe_O i.MX 6 internal
PCIe0 transmit
lane+
X1B69 X_PCIe0_TX- PCIe_O i.MX 6 internal
PCIe0 transmit
lane-
X1B70 X_PCIe0_nWAKE I/O VDD_3V3_LOGIC
PCIe0 wake
signal (low active)
X1B71 X_PCIe0_RX+ PCIe_I i.MX 6 internal
PCIe0 receive
lane+
X1B72 X_PCIe0_RX- PCIe_I i.MX 6 internal
PCIe0 receive
lane-
X1B74 X_PCIe0_CLK+ PCIe_O i.MX 6 internal PCIe0 clock lane+
X1B75 X_PCIe0_CLK- PCIe_O i.MX 6 internal PCIe0 clock lane-
Table 25: PCIe Interface Signal Location
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