Phytec phyFLEX-i.MX 6 - phyFLEX-optional Connector X2 Pinout (Row A)

phyFLEX
®
-i.MX 6 [PFL-A-XL1-xxx
16  PHYTEC Messtechnik GmbH 2013 L-773e_2
Pin # Signal ST Voltage Domain Description
X2A1 X_I2C1_SDA OC-BI VDD_3V3_LOGIC I2C1 data
X2A2 X_I2C1_SCL OC-BI VDD_3V3_LOGIC I2C1 clock
X2A3 reference-voltage REF_O VDD_3V3_LOGIC I2C1 reference voltage
X2A4 X_CAN0_TXD O VDD_3V3_LOGIC CAN0 transmit
X2A5 X_CAN0_RXD I VDD_3V3_LOGIC CAN0 receive
X2A6 GND - - Ground 0 V
X2A7 reference-voltage REF_O VDD_3V3_LOGIC CAN0 reference voltage
X2A8 X_HDMI0_SDA I/O VDD_3V3_LOGIC HDMI0 I
2
C data
X2A9 X_HDMI0_SCL I/O VDD_3V3_LOGIC HDMI0 I
2
C clock
X2A10 X_SATA0_TX+ LVDS_O i.MX 6 internal SATA0 transmit lane+
X2A11 X_SATA0_TX- LVDS_O i.MX 6 internal SATA0 transmit lane-
X2A12 GND - - Ground 0 V
X2A13 X_SATA0_RX+ LVDS_I i.MX 6 internal SATA0 receive lane+
X2A14 X_SATA0_RX- LVDS_I i.MX 6 internal SATA0 receive lane-
X2A15 X_SD1_D3 I/O VDD_SD1 SD1 data 3
X2A16 X_SD1_CMD O VDD_SD1 SD1 command
X2A17 X_SD1_CLK O VDD_SD1 SD1 clock
X2A18 GND - - Ground 0 V
X2A19 reference-voltage REF_O VDD_SD1 SD1 reference voltage
X2A20 X_SD1_nWP I VDD_SD1
SD1 write protection
(active low)
X2A21 X_SD1_nCD I VDD_SD1
SD1 card detection (active
low)
X2A22 X_SD1_D0 I/O VDD_SD1 SD1 data 0
X2A23 X_SD1_D1 I/O VDD_SD1 SD1 data 1
X2A24 GND - - Ground 0 V
X2A25 X_SD1_D2 I/O VDD_SD1 SD1 data 2
X2A26 N.C. - - Not connected
X2A27 N.C. - - Not connected
X2A28 N.C. - - Not connected
X2A29 N.C. - - Not connected
X2A30 GND - - Ground 0 V
X2A31 N.C. - - Not connected
X2A32 N.C. - - Not connected
X2A33 N.C. - - Not connected
X2A34 N.C. - - Not connected
X2A35 N.C. - - Not connected
X2A36 GND - - Ground 0 V
X2A37 N.C. - - Not connected
Table 5: Pinout of the phyFLEX-optional Connector X2, Row A
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