Phytec phyFLEX-i.MX 6 - Page 31

Pin Description
 PHYTEC Messtechnik GmbH 2013 L-773e_2
15
X1B46
RSVD - - reserved
X1B47 N.C. - - Not connected
X1B48 N.C. - - Not connected
X1B49 GND - Ground 0 V
X1B50 X_LVDS0_L0+ LVDS_O i.MX 6 internal LVDS0 data0+
X1B51 X_LVDS0_L0- LVDS_O i.MX 6 internal LVDS0 data0-
X1B52 X_LVDS0_nDISP_EN I/O VDD_3V3_LOGIC
LVDS0 display enable
(low active)
X1B53 X_LVDS0_L1+ LVDS_O i.MX 6 internal LVDS0 data1+
X1B54 X_LVDS0_L1- LVDS_O i.MX 6 internal LVDS0 data1-
X1B55 GND - - Ground 0 V
X1B56 X_LVDS0_L2+ LVDS_O i.MX 6 internal LVDS0 data2+
X1B57 X_LVDS0_L2- LVDS_O i.MX 6 internal LVDS0 data2-
X1B58
X_LVDS0_DISP_BL_P
WM
I/O VDD_3V3_LOGIC
LVDS0 backlight PWM
output
X1B59 X_LVDS0_L3+ LVDS_O i.MX 6 internal LVDS0 data3+
X1B60 X_LVDS0_L3- LVDS_O i.MX 6 internal LVDS0 data3-
X1B61 GND - - Ground 0 V
X1B62 X_LVDS0_CLK+ LVDS_O i.MX 6 internal LVDS0 clock+
X1B63 X_LVDS0_CL
K
- LVDS_O i.MX 6 internal LVDS0 clock-
X1B64 reference-voltage REF_O VDD_3V3_LOGIC LVDS0 reference voltage
X1B65 X_PCIe0_nPRSNT I/O VDD_3V3_LOGIC
PCIe0 present signal (low
active)
X1B66 reference-voltage REF_O VDD_3V3_LOGIC PCIe0 reference voltage
X1B67 GND - - Ground 0 V
X1B68 X_PCIe0_TX+ PCIe_O i.MX 6 internal PCIe0 transmit lane+
X1B69 X_PCIe0_TX- PCIe_O i.MX 6 internal PCIe0 transmit lane-
X1B70 X_PCIe0_nWAKE I/O VDD_3V3_LOGIC
PCIe0 wake signal (low
active)
X1B71 X_PCIe0_RX+ PCIe_I i.MX 6 internal PCIe0 receive lane+
X1B72 X_PCIe0_RX- PCIe_I i.MX 6 internal PCIe0 receive lane-
X1B73 GND - - Ground 0 V
X1B74 X_PCIe0_CLK+ PCIe_O i.MX 6 internal PCIe0 clock lane+
X1B75 X_PCIe0_CL
K
- PCIe_O i.MX 6 internal PCIe0 clock lane-
X1B76 X_BOOT0 IPU VDD_PM Boot configuration 0
X1B77 X_BOOT1 IPU VDD_PM Boot configuration 1
X1B78 X_BOOT2 IPU VDD_PM Boot configuration 2
X1B79 GND - - Ground 0 V
X1B80 RSVD - - reserved
Table 4: Pinout of the phyFLEX-fix Connector X1, Row B (continued)
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