Phytec phyFLEX-i.MX 6 - General Purpose I;Os; Table 27: Location of GPIO Pins

General Purpose I/O
 PHYTEC Messtechnik GmbH 2013 L-773e_2
55
9 General Purpose I/Os
The phyFLEX bus provides 11 GPIO signals. Table 27 shows the
location of the GPIO pins on the phyFLEX-Connector, as well as the
corresponding ports of the i.MX 6.
Pin # Signal ST Voltage Domain Description
X1A54 X_GPIO0 I/O VDD_3V3_LOGIC
General purpose
input/output 0
(GPIO5_8 of i.MX 6)
X1A55 X_GPIO1 I/O VDD_3V3_LOGIC
General purpose
input/output 1
(GPIO5_7 of i.MX 6)
X1A56 X_GPIO2 I/O VDD_3V3_LOGIC
General purpose
input/output 2
(GPIO4_18 of i.MX 6)
X1A57
reference-
voltage
REF_O VDD_3V3_LOGIC GPIO reference voltage
X1A59 X_GPIO3 I/O VDD_3V3_LOGIC
General purpose
input/output 3
(GPIO4_19 of i.MX 6)
X1A60 X_GPIO4 I/O VDD_3V3_LOGIC
General purpose
input/output 4
(GPIO1_6 of i.MX 6)
X1A61 X_GPIO5 I/O VDD_3V3_LOGIC
General purpose
input/output 5
(GPIO1_9 of i.MX 6)
X1A62 X_GPIO6 I/O VDD_3V3_LOGIC
General purpose
input/output 6
(GPIO7_12 of i.MX 6)
Table 27: Location of GPIO Pins
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